UPD72852A データシートの表示（PDF） - NEC => Renesas Technology

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UPD72852A

IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI

NEC => Renesas Technology 

µPD72852A

1.3 Control Pins

Name

PC0

PC1

PC2

CMC

Pin No.

26

27

28

30

RESETB

55

FNSel

62

SPD

61

BDB

61

I/O

Function

I

Power class set input

I

This pin status will be loaded to Pwr_class bit which allocated to PHY register 4H.

I

IEEE1394a-2000 chapter [4.3.4.1]

I

Configuration manager capable setting

This pin status will be loaded to Contender bit which allocated to PHY register 4H.

0: Non contender

1: Contender

I

Power-on reset input

Connect to GND through a 0.1 µF capacitor.

0: Reset

1: Normal

I

Function Select

0: #61 acts as SPD

1: #61 acts as BDB

I

Speed select ( When FNSel set to 0 ; µPD72852A compliant)

0: MAX. S200

1: MAX. S400

O

BIAS Detected (Logical Inverse)

0: BIAS is detected after suspend debounce timer.

1: BIAS is not detected.

1.4 IC

Name

IC(AL)

Pin No.

29, 51

IC(DL)

3

I/O

Function

-

Internally Connected (Low Clamped)

Connect to GND.

-

Internally Connected (Low Clamped)

Connect to GND.

1.5 Power Supply Pins

Name

AVDD

AGND

DVDD

DGND

Pin No.

I/O

25, 31, 40, 47, 54

-

Analog power

24, 33, 35, 42, 49, 52, 53

-

Analog GND

4, 10, 20, 56, 60

-

Digital VDD

1, 7, 13, 16, 21, 57, 64

-

Digital GND

Function

8

Data Sheet S16725EJ2V0DS

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