UPD72852A データシートの表示（PDF） - NEC => Renesas Technology

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UPD72852A

IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI

NEC => Renesas Technology 

BLOCK DIAGRAM

CMC

PC0

PC1

PC2

SUS/RES

LREQ

LPS

DIRECT

SCLK

LKON

CTL0

CTL1

D0

D1

D2

D3

D4

D5

D6

D7

Link

Interface

I/O

BDB

RESETB

CPS

Cable

Power

Status

µPD72852A

Arbitration

and Control

State Machine

Logic

Receive Data

Decoder and

Retimer

Transmit Data

Encoder

Cable

Port0

Cable

Port1

TpA0p

TpA0n

TpB0p

TpB0n

TpA1p

TpA1n

TpB1p

TpB1n

Voltage

and

Current

Generator

Crystal

Oscillator

PLL

System

and

Transmit

Clock

Generator

TpBias0

TpBias1

RI1

XI

XO

2

Data Sheet S16725EJ2V0DS

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