UPD72852A データシートの表示（PDF） - NEC => Renesas Technology
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UPD72852A Datasheet PDF : 48 Pages
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µPD72852A
1. PIN FUNCTIONS
1.1 Cable Interface Pins
Name
Pin No.
I/O
TpA0p
39
I/O
TpA0n
38
I/O
TpB0p
37
I/O
TpB0n
36
I/O
TpA1p
46
I/O
TpA1n
45
I/O
TpB1p
44
I/O
TpB1n
43
I/O
SUS/RES
19
I
CPS
32
I
1.2 Link Interface Pins
Name
Pin No.
I/O
D0
8
I/O
D1
9
I/O
D2
11
I/O
D3
12
I/O
D4
14
I/O
D5
15
I/O
D6
17
I/O
D7
18
I/O
CTL0
5
I/O
CTL1
6
I/O
LREQ
63
I
SCLK
2
O
LPS
59
I
LKON
58
O
DIRECT
50
I
Function
Port 0 twisted pair cable A positive phase I/O
Port 0 twisted pair cable A negative phase I/O
Port 0 twisted pair cable B positive phase I/O
Port 0 twisted pair cable B negative phase I/O
Port 1 twisted pair cable A positive phase I/O
Port 1 twisted pair cable A negative phase I/O
Port 1 twisted pair cable B positive phase I/O
Port 1 twisted pair cable B negative phase I/O
Suspend/Resume function select
1: Suspend/Resume on (IEEE1394a-2000 compliant)
0: Suspend/Resume off (P1394a draft 1.3 compliant)
Cable power status
Connect to the cable through a 390 kΩ resistor and to GND through a 100 kΩ resistor.
0: Cable power fail
1: Cable power on
Function
Data input/output (bit 0)
Data input/output (bit 1)
Data input/output (bit 2)
Data input/output (bit 3)
Data input/output (bit 4)
Data input/output (bit 5)
Data input/output (bit 6)
Data input/output (bit 7)
Link interface control (bit 0)
Link interface control (bit 1)
Link request input
Link control output clock
LPS 1: 49.152 MHz output
LPS 0: Clamp to 0 (The clock signal will be output within 25 µsec after change to “0”)
Link power status input
0: Link power off
1: Link power on (PHY/Link direct connection)
Link-on signal output
Link-on signal is 6.144 MHz clock output.
Please refer to 4.2 Link-on Indication.
PHY/Link isolation barrier control input
0: Isolation barrier
1: PHY/Link direct connection
Data Sheet S16725EJ2V0DS
7
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