UPD72852A データシートの表示（PDF） - NEC => Renesas Technology

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UPD72852A

IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI

NEC => Renesas Technology 

µPD72852A

CONTENTS

1. PIN FUNCTIONS..................................................................................................................................... 7

1.1 Cable Interface Pins ........................................................................................................................ 7

1.2 Link Interface Pins .......................................................................................................................... 7

1.3 Control Pins ..................................................................................................................................... 8

1.4 IC ....................................................................................................................................................... 8

1.5 Power Supply Pins .......................................................................................................................... 8

1.6 Other Pins ........................................................................................................................................ 9

2. PHY REGISTERS .................................................................................................................................. 10

2.1 Complete Structure for PHY Registers ....................................................................................... 10

2.2 Port Status Page (Page 000) ........................................................................................................ 13

2.3 Vendor ID Page (Page 001)........................................................................................................... 14

2.4 Vendor Dependent Page (Page 111 : Port_select 0000)............................................................ 14

2.5 Vendor Dependent Page (Page 111 : Port_select 0001)............................................................ 15

3. INTERNAL FUNCTION.......................................................................................................................... 16

3.1 Link Interface ................................................................................................................................. 16

3.1.1 Connection Method ............................................................................................................................... 16

3.1.2 LPS (Link Power Status) ....................................................................................................................... 16

3.1.3 LREQ, CTL0, CTL1 and D0-D7 Pins..................................................................................................... 16

3.1.4 SCLK..................................................................................................................................................... 16

3.1.5 LKON .................................................................................................................................................... 17

3.1.6 DIRECT................................................................................................................................................. 17

3.1.7 Isolation Barrier ..................................................................................................................................... 17

3.2 Cable Interface............................................................................................................................... 19

3.2.1 Connections .......................................................................................................................................... 19

3.2.2 Cable Interface Circuit........................................................................................................................... 20

3.2.3 Unused Ports ........................................................................................................................................ 20

3.2.4 CPS....................................................................................................................................................... 20

3.3 Suspend/Resume .......................................................................................................................... 20

3.3.1 Suspend/Resume On Mode (SUS/RES = “H”)...................................................................................... 20

3.3.2 Suspend/Resume Off Mode (SUS/RES = “L”) ...................................................................................... 20

3.4 PLL and Crystal Oscillation Circuit ............................................................................................. 21

3.4.1 Crystal Oscillation Circuit ...................................................................................................................... 21

3.4.2 PLL........................................................................................................................................................ 21

3.5 CMC ................................................................................................................................................ 21

3.6 PC0-PC2 ......................................................................................................................................... 21

3.7 RESETB .......................................................................................................................................... 21

3.8 RI1 ................................................................................................................................................... 21

4. PHY/LINK INTERFACE ......................................................................................................................... 22

4.1 Initialization of Link Power Status (LPS) and PHY/Link Interface............................................ 22

4.2 Link-on Indication ......................................................................................................................... 23

4.3 PHY/Link Interface Operation (CTL0, CTL1, LREQ, D0-D7) ...................................................... 24

4.3.1 CTL0, CTL1 .......................................................................................................................................... 24

4.3.2 LREQ .................................................................................................................................................... 24

Data Sheet S16725EJ2V0DS

5

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