UPD72852A データシートの表示（PDF） - NEC => Renesas Technology

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UPD72852A

IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI

NEC => Renesas Technology 

PIN NAME

AGND

AVDD

CMC

CPS

CTL0

CTL1

D0-D7

DGND

DIRECT

DVDD

FNSel

IC(AL)

IC(DL)

LKON

LPS

LREQ

PC0-PC2

RESETB

RI1

SCLK

SPD/BDB

SUS/RES

TpA0n

TpA0p

TpA1n

TpA1p

TpB0n

TpB0p

TpB1n

TpB1p

TpBias0

TpBias1

XI

XO

: Analog GND

: Analog Power

: Configuration Manager Capable

: Cable Power Status

: Link Interface Control (bit 0)

: Link Interface Control (bit 1)

: Data Input/Output

: Digital GND

: PHY/Link Isolation Barrier Control Input

: Digital VDD

: Function Select

: Internally Connected (Low Clamped)

: Internally Connected (Low Clamped)

: Link-on Signal Output

: Link Power Status Input

: Link Request Input

: Power Class Set Input

: Power-on Reset Input

: Reference Power Set, Connect Resistor 1

: Link Control Output Clock

: Speed Select input / BIAS Detected output

: Suspend/Resume Function Select

: Port 0 Twisted Pair Cable A Negative Phase I/O

: Port 0 Twisted Pair Cable A Positive Phase I/O

: Port 1 Twisted Pair Cable A Negative Phase I/O

: Port 1 Twisted Pair Cable A Positive Phase I/O

: Port 0 Twisted Pair Cable B Negative Phase I/O

: Port 0 Twisted Pair Cable B Positive Phase I/O

: Port 1 Twisted Pair Cable B Negative Phase I/O

: Port 1 Twisted Pair Cable B Positive Phase I/O

: Port 0 Twisted Pair Output

: Port 1 Twisted Pair Output

: Crystal Oscillator Connection XI

: Crystal Oscillator Connection XO

µPD72852A

4

Data Sheet S16725EJ2V0DS

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