SCN2651CC1N28 データシートの表示（PDF） - Philips Electronics
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SCN2651CC1N28 Datasheet PDF : 15 Pages
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Philips Semiconductors
Programmable communications interface (PCI)
Product specification
SCN2651
Table 8. Status Register (SR)
SR7
SR6
SR5
Data Set
Ready
Data Carrier
Detect
FE/SYN
Detect
0 = DSR input
is high
1 = DSR input
is low
0 = DCD input
is high
1 = DCD input
is low
Async:
0 = Normal
1 = Framing
ERROR
Sync:
0 = Normal
1 = SYN char
detected
SR4
Overrun
0 = Normal
1 = Overrun
error
SR3
SR2
PE/DLE
Detect
TxEMT/
DSCHG
Async:
0 = Normal
1 = Parity error
Sync:
0 = Normal
1 = Parity
error or
DLE char
received
0 = Normal
1 = Change in
DSR or
DCD, or
transmit
shift
register is
empty
SR1
RxRDY
0 = Receive
holding
register
empty
1 = Receive
holding
register
has data
SR0
TxRDY
0 = Transmit
holding
register
busy
1 = Transmit
holding
register
empty
Setting CR4 causes the error flags in the status register (SR3, SR4,
and SR5) to be cleared. This is a one time command. There is no
internal latch for this bit.
The PCI can operate in one of four submodes within each major
mode (synchronous or asynchronous). The operational submode is
determined by CR7 and CR6. CR7 – CR6 = 00 is the normal mode,
with the transmitter and receiver operating independently in
accordance with the mode and status register instructions.
In asynchronous mode, CR7 – CR6 = 01 places the PCI in the
automatic echo mode. Clocked, regenerated received data are
automatically directed to the TxD line while normal receiver
operation continues. The receiver must be enabled (CR2 = 1), but
the transmitter need not be enabled. CPU to receiver
communications continues normally, but the CPU to transmitter link
is disabled. Only the first character of a break condition is echoed.
The TxD output will go high until the next valid start is detected.
The following conditions are true while in automatic echo mode:
1. Data assembled by the receiver are automatically placed in the
transmit holding register and retransmitted by the transmitter on
the TxD output.
2. The transmitter is clocked by the receive clock.
3. TxRDY output = 1.
4. The TxEMT/DSCHG pin will reflect only the data set change
condition.
5. The TxEN command (CR0) is ignored.
In synchronous mode, CR7 – CR6 = 01 places the PCI in the
automatic SYN/DLE stripping mode. The exact action taken
depends on the setting of bits MR17 and MR16:
1. In the non-transparent, single SYN mode (MR17 – MR16 = 10),
characters in the data stream matching SYN1 are not transferred
to the receive data holding register (RHR).
2. In the non-transparent, double SYN mode (MR17 – MR16 = 00),
characters in the data stream matching SYN1, or SYN2 if
immediately preceded by SYN1, are not transferred the RHR.
However, only the first SYN1 of an SYN1 – SYN1 pair is
stripped.
3. In transparent mode (MR16 = 1), character in the data stream
matching DLE, or SYN1 if immediately preceded by DLE, are not
transferred to the RHR. However, only the first DLE of a DLE–
DLE pair is stripped.
Note that automatic stripping mode does not affect the setting of the
DLE detect and SYN detect status bits (SR3 and SR5).
Two diagnostic submodes can also be configured. In local loopback
mode (CR7 – CR6 = 10), the following loops are connected
internally:
1. The transmitter output is connected to the receiver input.
2. DTR is connected to DCD and RTS is connected to CTS.
3. The receiver is clocked by the transmit clock.
4. The DTR, RTS and TxD outputs are held high.
5. The CTS, DCD, DSR and RxD inputs are ignored.
Additional requirements to operate in the local loopback mode are
that CR0 (TxEN), CR1 (DTR), and CR5 (RTS) must be set to 1.
CR2 (RxEN) is ignored by the PCI.
The second diagnostic mode is the remote loopback mode (CR7 –
CR6 = 11). In this mode:
1. Data assembled by the receiver are automatically placed in the
transmit holding register and retransmitted by the transmitter on
the TxD output.
2. The transmitter is clocked by the receive clock.
3. No data is sent to the local CPU, but he error status conditions
(PE, OE, FE) are set.
4. The RxRDY, TxRDY, and TxEMT/DSCHG outputs are held high.
5. CR0 (TxEN) is ignored.
6. All other signals operate normally.
Status Register
The data contained in the status register (as shown in Table 8)
indicate receiver and transmitter conditions and modem/data set
status.
SR0 is the transmitter ready (TxRDY) status bit. It, and its
corresponding output, are valid only when the transmitter is enabled.
If equal to 0, it indicates that the transmit data holding register has
been loaded by the CPU and the data has not been transferred to
the transmit shift register. If set equal to 1, it indicates that the
Holding Register is ready to accept data from the CPU. This bit is
initially set when the transmitter is enabled by CR0, unless a
character has previously been loaded into the holding register. It is
not set when the automatic echo or remote loopback modes are
programmed. When this bit is set, the TxRDY output pin is low. In
the automatic echo and remote loopback modes, the output is held
high.
SR1, the receiver ready (RxRDY) status bit, indicates the condition
of the receive data holding register. If set, it indicates that a
1994 Apr 27
9
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