SCN2651CC1N28 データシートの表示（PDF） - Philips Electronics
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SCN2651CC1N28 Datasheet PDF : 15 Pages
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Philips Semiconductors
Programmable communications interface (PCI)
Product specification
SCN2651
INTERFACE SIGNALS
The PCI interface signals can be grouped into two types: the
CPU-related signals (shown in Table 2), which interface the
SCN2651 to the microprocessor system, and the device-related
signals (shown in Table 3), which are used to interface to the
communications device or system.
OPERATION
The functional operation of the SCN2651 is programmed by a set of
control words supplied by the CPU. These control words specify
items such as synchronous or asynchronous mode, baud rate,
number of bits per character, etc. The programming procedure is
described in the PCI programming section of the data sheet.
After programming, the PCI is ready to perform the desired
communications functions. The receiver performs serial to parallel
conversion of data received from a modem or equivalent device.
The transmitter converts parallel data received from the CPU to a
serial bit stream. These actions are accomplished within the
framework specified by the control words.
Receiver
The SCN2651 is conditioned to receive data when the DCD input is
low and the RxEN bit in the command register is true. In the
asynchronous mode, the receiver looks for a high to low transition of
the start bit on the RxD input line. If a transition is detected, the
state of the RxD line is sampled again after a delay of one-half of a
bit-time. If RxD is now high, the search for a valid start bit is begun
again. If RxD is still low, a valid start bit is assumed and the receiver
continues to sample the input line at one bit time intervals until the
proper number of data bits, the parity bit, and one stop bit(s) have
been assembled. The data is then transferred to the receive data
holding register, the RxRDY bit in the status register is set, and the
RxRDY output is asserted. If the character length is less than 8 bits,
the high order unused bits in the holding register are set to zero.
The parity error, framing error, and overrun error status bits are
strobed into the status register on the positive going edge of RxC
corresponding to the received character boundary. If a break
condition is detected (RxD is low for the entire character as well as
the stop bit[s]), only one character consisting of all zeros (with the
FE status bit set) will be transferred to the holding register. The RxD
input must return to a high condition before a search for the next
start bit begins.
When the PCI is initialized into the synchronous mode, the receiver
first enters the hunt mode on a 0 to 1 transition of RxEN (CR2). In
this mode, as data is shifted into the receiver shift register a bit at a
time, the contents of the register are compared to the contents of the
SYN1 register. If the two are not equal, the next bit is shifted in and
the comparison is repeated. When the two registers match, the
hunt mode is terminated and character assembly mode begins. If
single SYN operation is programmed, the SYN detect status bit is
set. If double SYN operation is programmed, the first character
assembled after SYN1 must be SYN2 in order for the SYN detect bit
to be set. Otherwise, the PCI returns to the hunt mode. (Note that
the sequence SYN1–SYN1–SYN2 will not achieve synchronization.)
When synchronization has been achieved, the PCI continues to
assemble characters and transfer them to the holding register,
setting the RxRDY status bit and asserting the RxRDY output each
time a character is transferred. The PE and OE status bits are set
as appropriate. Further receipt of the appropriate SYN sequence
sets the SYN detect status bit. If the SYN stripping mode is
Table 2.
PIN NAME
VCC
GND
RESET
A1 – A0
R/W
CE
D7 – D0
TxRDY
RxRDY
TxEMT/DS
CHG
CPU-Related Signals
PIN INPUT/
NO. OUTPUT
FUNCTION
26
I
+5V supply input
4
I
Ground
A high on this input performs a master reset on the SCN2651. This signal asynchronously terminates any
21
I
device activity and clears the mode, command and status registers. The device assumes the idle state
and remains there until initialized with the appropriate control words.
10, 12
13
I
Address lines used to select internal PCI registers.
I
Read command when low, write command when high.
Chip enable command. When low, indicates that control and data lines to the PCI are valid and that the
11
I
operation specified by the RW, A1 and A0 inputs should be performed. When high, places the D0–D7 lines
in the 3-State condition.
8, 7, 6,
5, 2, 1,
28, 27
I/O
8-bit, three-state data bus used to transfer commands, data and status between PCI and the CPU. D0 is
the least significant bit, D7 the most significant bit.
This output is the complement of status register bit SR0. When low, it indicates that the transmit data
15
O
holding register (THR) is ready to accept a data character from the CPU. It goes high when the data
character is loaded. This output is valid only when the transmitter is enabled. It is an open drain output
which can be used as an interrupt to the CPU.
This output is the complement of status register bit SR1. When low, it indicates that the receive data
14
O
holding register (RHR) has a character ready for input to the CPU. It goes high when the RHR is read by
the CPU, and also when the receiver is disabled. It is an open drain output which can be used as an
interrupt to the CPU.
This output is the complement of status register bit SR2. When low, it indicates that the transmitter has
completed serialization of the last character loaded by the CPU, or that a change of state of the DSR or
18
O
DCD inputs has occurred. This output goes high when the status register is read by the CPU, if the
TxEMT condition does not exist. Otherwise, the THR must be loaded by the CPU for this line to go high.
It is an open drain output which can be used as an interrupt to the CPU.
1994 Apr 27
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