NT512D72S4PA0GR データシートの表示（PDF） - Nanya Technology

部品番号

コンポーネント説明

一致するリスト

NT512D72S4PA0GR

184pin One Bank Registered DDR SDRAM MODULE Based on 64Mx4 DDR SDRAM

Nanya Technology 

NT512D72S4PA0GR

512MB : 64M x 72

Registered DDR SDRAM DIMM

DC Electrical Characteristics and Operating Conditions

( TA = 0 °C ~ 70 °C ; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics)

Symbol

VDD

VDDQ

VSS , VSSQ

VREF

VTT

VIH(DC)

VIL(DC)

VIN(DC)

VID(DC)

Parameter

Supply Voltage

I/O Supply Voltage

Supply Voltage, I/O Supply Voltage

/O Reference Voltage

I/O Termination Voltage (System)

Input High (Logic1) Voltage

Input Low (Logic0) Voltage

Input Voltage Level, CK and CK Inputs

Input Differential Voltage, CK and CK Inputs

Min

Max

2.3

2.7

2.3

2.7

0

0

0.49 x VDDQ 0.51 x VDDQ

VREF – 0.04 VREF + 0.04

VREF + 0.15 VDDQ + 0.3

-0.3

VREF- 0.15

-0.3

VDDQ + 0.3

0.30

V DDQ + 0.6

Units

V

V

V

V

V

V

V

V

V

Notes

1

1

1,2

1,3

1

1

1

1,4

Input Leakage Current

II

Any input 0V ≤ VIN ≤ VDD; (All other pins not under test = 0V)

-5

5

uA

1

Output Leakage Current

IOZ

(DQs are disabled; 0V ≤ Vout ≤ VDDQ

Output High Current

IOH

(VOUT = VDDQ -0.373V, min VREF , min VTT )

-5

-16.8

5

uA

1

-

mA

1

Output Low Current

IOL

(VOUT = 0.373, max VREF , max VTT )

16.8

-

mA

1

1. Inputs are not recognized as valid until VREF stabilizes.

2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak

noise on VREF may not exceed 2% of the DC value.

3. VTT is not applied directly to the DIMM. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF ,

and must track variations in the DC level of VREF .

4. VID is the magnitude of the difference between the input level on CK and the input level on CK .

Preliminary 08/01

8

© NANYA TECHNOLOGY CORP.

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Share Link: