NT512D72S4PA0GR データシートの表示（PDF） - Nanya Technology
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NT512D72S4PA0GR Datasheet PDF : 14 Pages
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NT512D72S4PA0GR
512MB : 64M x 72
Registered DDR SDRAM DIMM
184pin One Bank Registered DDR SDRAM MODULE Based on 64Mx4 DDR SDRAM
Features
• 184-Pin Registered 8-Byte Dual In-Line Memory Module
• 64Mx72 Double Data Rate (DDR) SDRAM DIMM
• Performance :
PC1600
PC2100
Speed Sort
- 8B - 75B - 7K
DIMM CAS Latency
3
3.5
3
f CK Clock Frequency
100 133 133
t CK Clock Cycle
10
7.5
7.5
f DQ DQ Burst Frequency 200 266 266
• Intended for 100 MHz and 133 MHz applications
• Inputs and outputs are SSTL-2 compatible
• VDD = 2.5Volt ± 0.2, VDDQ = 2.5Volt ± 0.2
• Single Pulsed RAS interface
• SDRAMs have 4 internal banks for concurrent operation
• Module has one physical bank
• Differential clock inputs
• Data is read or written on both clock edges
Unit
MHz
ns
MHz
• Bi-directional data strobe with one clock cycle preamble and
one-half clock post-amble
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM CAS Latency: 3, 3.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 13/11/2 Addressing (row/column/bank)
• 7.8 µs Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 66-pin TSOP Type II Package
Description
NT512D72S4PA0GR is a registered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),
organized as a one-bank high-speed memory array. The 64Mx72 module is a single-bank DIMM that uses eighteen 64Mx4 DDR
SDRAMs in 400 mil TSOP packages. The DIMM achieves high-speed data transfer rates of up to 266MHz. The DIMM is intended for use
in applications operating from 100 MHz to 133 MHz clock speeds with data rates of 200 to 266 MHz. Clock enable CKE0 controls all
devices on the DIMM.
Prior to any access operation, the device CAS latency and burst type/ length/operation type must be programmed into the DIMM by
address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.
These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common
design files minimizes electrical variation between suppliers.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD
data are programmed and locked during module assembly. The last 128 bytes are available to the customer.
All NANYA 184 DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.
Ordering Information
Part Number
NT512D72S4PA0GR -7K
NT512D72S4PA0GR -75B
NT512D72S4PA0GR - 8B
Speed
Component
143MHz (7ns @ CL = 2.5 )
133MHz (7.5ns @ CL= 2 )
DDR266A
133MHz (7.5ns @ CL= 2.5 )
100MHz (10ns @ CL = 2 )
DDR266B
125MHz (8ns @ CL = 2.5 )
100MHz (10ns @ CL = 2 )
DDR200
Module
PC2100
PC2100
PC1600
Organization
64Mx72
Leads
Gold
Power
2.5V
Preliminary 08/01
1
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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