ADSP-2191MKCA-160 データシートの表示（PDF） - Analog Devices

部品番号

コンポーネント説明

一致するリスト

ADSP-2191MKCA-160

DSP Microcomputer

Analog Devices 

ADSP-2191M

different mechanisms to generate a 24-bit address for each bus.

The DSP has three functions that support access to the full

memory map.

• The DAGs generate 24-bit addresses for data fetches from

the entire DSP memory address range. Because DAG

index (address) registers are 16 bits wide and hold the

lower 16 bits of the address, each of the DAGs has its own

8-bit page register (DMPGx) to hold the most significant

eight address bits. Before a DAG generates an address,

the program must set the DAG’s DMPGx register to the

appropriate memory page.

• The Program Sequencer generates the addresses for

instruction fetches. For relative addressing instructions,

the program sequencer bases addresses for relative jumps,

calls, and loops on the 24-bit Program Counter (PC). In

direct addressing instructions (two-word instructions),

the instruction provides an immediate 24-bit address

value. The PC allows linear addressing of the full 24-bit

address range.

• For indirect jumps and calls that use a 16-bit DAG

address register for part of the branch address, the

Program Sequencer relies on an 8-bit Indirect Jump page

(IJPG) register to supply the most significant eight

address bits. Before a cross page jump or call, the program

must set the program sequencer’s IJPG register to the

appropriate memory page.

The ADSP-2191M has 1K word of on-chip ROM that holds boot

routines. If peripheral booting is selected, the DSP starts

executing instructions from the on-chip boot ROM, which starts

the boot process from the selected peripheral. For more informa-

tion, see “Booting Modes” on page 11. The on-chip boot ROM

is located on Page 255 in the DSP’s memory space map.

External (Off-Chip) Memory

Each of the ADSP-2191M’s off-chip memory spaces has a

separate control register, so applications can configure unique

access parameters for each space. The access parameters include

read and write wait counts, waitstate completion mode, I/O clock

divide ratio, write hold time extension, strobe polarity, and data

bus width. The core clock and peripheral clock ratios influence

the external memory access strobe widths. For more information,

see “Clock Signals” on page 11. The off-chip memory spaces are:

• External memory space (MS3–0 pins)

• I/O memory space (IOMS pin)

• Boot memory space (BMS pin)

All of these off-chip memory spaces are accessible through the

External Port, which can be configured for data widths of

8 or 16 bits.

External Memory Space

External memory space consists of four memory banks. These

banks can contain a configurable number of 64K word pages. At

reset, the page boundaries for external memory have Bank0

containing pages 1−63, Bank1 containing pages 64−127, Bank2

containing pages 128−191, and Bank3 that contains pages

192−254. The MS3–0 memory bank pins select Banks 3–0,

respectively. The external memory interface is byte-addressable

and decodes the 8 MSBs of the DSP program address to select

one of the four banks. Both the ADSP-219x core and DMA-capa-

ble peripherals can access the DSP’s external memory space.

I/O Memory Space

The ADSP-2191M supports an additional external memory

called I/O memory space. This space is designed to support

simple connections to peripherals (such as data converters and

external registers) or to bus interface ASIC data registers. I/O

space supports a total of 256K locations. The first 8K addresses

are reserved for on-chip peripherals. The upper 248K addresses

are available for external peripheral devices. The DSP’s instruc-

tion set provides instructions for accessing I/O space. These

instructions use an 18-bit address that is assembled from an

8-bit I/O page (IOPG) register and a 10-bit immediate value

supplied in the instruction. Both the ADSP-219x core and a Host

(through the Host Port Interface) can access I/O memory space.

Boot Memory Space

Boot memory space consists of one off-chip bank with 63 pages.

The BMS memory bank pin selects boot memory space. Both

the ADSP-219x core and DMA-capable peripherals can access

the DSP’s off-chip boot memory space. After reset, the DSP

always starts executing instructions from the on-chip boot ROM.

Depending on the boot configuration, the boot ROM code can

start booting the DSP from boot memory. For more information,

see “Booting Modes” on page 11.

Interrupts

The interrupt controller lets the DSP respond to 17 interrupts

with minimum overhead. The controller implements an interrupt

priority scheme as shown in Table 1. Applications can use the

unassigned slots for software and peripheral interrupts.

Table 2 shows the ID and priority at reset of each of the periph-

eral interrupts. To assign the peripheral interrupts a different

priority, applications write the new priority to their correspond-

ing control bits (determined by their ID) in the Interrupt Priority

Control register. The peripheral interrupt’s position in the

IMASK and IRPTL register and its vector address depend on its

priority level, as shown in Table 1. Because the IMASK and

IRPTL registers are limited to 16 bits, any peripheral interrupts

–6–

REV. 0

Share Link: