ADSP-2191MKCA-160 データシートの表示（PDF） - Analog Devices

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ADSP-2191MKCA-160

DSP Microcomputer

Analog Devices 

Three programmable interval timers generate periodic inter-

rupts. Each timer can be independently set to operate in one of

three modes:

• Pulse Waveform Generation mode

• Pulsewidth Count/Capture mode

• External Event Watchdog mode

Each timer has one bidirectional pin and four registers that

implement its mode of operation: A 7-bit configuration register,

a 32-bit count register, a 32-bit period register, and a 32-bit

pulsewidth register. A single status register supports all three

timers. A bit in each timer’s configuration register enables or

disables the corresponding timer independently of the others.

Memory Architecture

The ADSP-2191M DSP provides 64K words of on-chip SRAM

memory. This memory is divided into four 16K blocks located

on memory Page 0 in the DSP’s memory map. In addition to the

ADSP-2191M

internal and external memory space, the ADSP-2191M can

address two additional and separate off-chip memory spaces: I/O

space and boot space.

As shown in Figure 2, the DSP’s two internal memory blocks

populate all of Page 0. The entire DSP memory map consists of

256 pages (Pages 0−255), and each page is 64K words long.

External memory space consists of four memory banks (banks

0–3) and supports a wide variety of SRAM memory devices. Each

bank is selectable using the memory select pins (MS3–0) and has

configurable page boundaries, waitstates, and waitstate modes.

The 1K word of on-chip boot-ROM populates the top of

Page 255 while the remaining 254 pages are addressable off-chip.

I/O memory pages differ from external memory pages in that I/O

pages are 1K word long, and the external I/O pages have their

own select pin (IOMS). Pages 0–7 of I/O memory space reside

on-chip and contain the configuration registers for the peripher-

als. Both the core and DMA-capable peripherals can access the

DSP’s entire memory map.

INTERNAL

MEMORY

EXTERNAL

MEMORY

(16- BIT)

INTERNAL

MEMORY

64K WORD

MEMORY

PAGES

PAGE 255

RESERVED

BOOT ROM, 24-BIT

LOGICAL

ADDRESS

0؋FF FFFF

0؋FF 0400

0؋FF 03FF

0؋FF 0000

PAGES 192–254

BANK3

(MS3)

0؋C0 0000

PAGES 128–191

BANK2

(MS2)

PAGES 64–127

BANK1

(MS1)

0؋80 0000

0؋40 0000

PAGES 1–63

BANK0

(MS0)

BLOCK3, 16-BIT

BLOCK2, 16-BIT

PAGE 0

BLOCK1, 24-BIT

BLOCK0, 24-BIT

0؋01 0000

0؋00 C000

0؋00 8000

0؋00 4000

0؋00 0000

Figure 2. Memory Map

Internal (On-Chip) Memory

The ADSP-2191M’s unified program and data memory space

consists of 16M locations that are accessible through two 24-bit

address buses, the PMA and DMA buses. The DSP uses slightly

LOWER PAGE BOUNDARIES

ARE CONFIGURABLE FOR

BANKS OF EXTERNAL MEMORY.

BOUNDARIES SHOWN ARE

BANK SIZES AT RESET.

MEMORY SELECTS (MS)

FOR PORTIONS OF THE

MEMORY MAP APPEAR

WITH THE SELECTED

MEMORY.

BOOT MEMORY

16-BIT

(BMS)

64K WORD

LOGICAL

ADDRESS

0؋FE FFFF

PAGES 1–254

0؋01 0000

I/O MEMORY

16- BIT

1K WORD

PAGES 8–255

1K WORD

PAGES 0–7

LOGICAL

ADDRESS

0؋FF 3FF

EXTERNAL

(IOMS)

INTERNAL

0؋08 000

0؋07 3FF

0؋00 000

8-BIT 10-BIT

REV. 0

–5–

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