ADSP-2191MKCA-160 データシートの表示（PDF） - Analog Devices

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ADSP-2191MKCA-160

DSP Microcomputer

Analog Devices 

ADSP-2191M

To exit Power-Down Core/Peripherals mode, the DSP responds

to an interrupt and (after 500 cycles to restabilize the PLL)

resumes executing instructions with the instruction after the

IDLE.

Clock Signals

The ADSP-2191M can be clocked by a crystal oscillator or a

buffered, shaped clock derived from an external clock oscillator.

If a crystal oscillator is used, the crystal should be connected

across the CLKIN and XTAL pins, with two capacitors and a

1 M Ω shunt resistor connected as shown in Figure 3. Capacitor

values are dependent on crystal type and should be specified by

the crystal manufacturer. A parallel-resonant, fundamental fre-

quency, microprocessor-grade crystal should be used for this

configuration.

If a buffered, shaped clock is used, this external clock connects

to the DSP’s CLKIN pin. CLKIN input cannot be halted,

changed, or operated below the specified frequency during

normal operation. When an external clock is used, the XTAL

input must be left unconnected.

The DSP provides a user-programmable 1؋ to 32؋ multiplica-

tion of the input clock, including some fractional values, to

support 128 external to internal (DSP core) clock ratios. The

MSEL6–0, BYPASS, and DF pins decide the PLL multiplication

factor at reset. At runtime, the multiplication factor can be con-

trolled in software. The combination of pullup and pull-down

resistors in Figure sets up a core clock ratio of 6:1, which

produces a 150 MHz core clock from the 25 MHz input. For

other clock multiplier settings, see the ADSP-219x/2191 DSP

Hardware Reference.

The peripheral clock is supplied to the CLKOUT pin.

All on-chip peripherals for the ADSP-2191M operate at the rate

set by the peripheral clock. The peripheral clock is either equal

to the core clock rate or one-half the DSP core clock rate. This

selection is controlled by the IOSEL bit in the PLLCTL register.

The maximum core clock is 160 MHz and the maximum periph-

eral clock is 80 MHz—the combination of the input clock and

core/peripheral clock ratios may not exceed these limits.

Reset

The RESET signal initiates a master reset of the ADSP-2191M.

The RESET signal must be asserted during the powerup

sequence to assure proper initialization. RESET during initial

powerup must be held long enough to allow the internal clock to

stabilize.

The powerup sequence is defined as the total time required for

the crystal oscillator circuit to stabilize after a valid VDD is applied

to the processor, and for the internal phase-locked loop (PLL) to

lock onto the specific crystal frequency. A minimum of 100 µs

ensures that the PLL has locked, but does not include the crystal

oscillator start-up time. During this powerup sequence the

RESET signal should be held low. On any subsequent resets, the

RESET signal must meet the minimum pulsewidth specifica-

tion, tWRST.

1M⍀

VDD

VDD

RUNTIME

PF PIN I/O

25MHz

CLKIN

XTAL

CLKOUT

MSEL0 (PF0)

ADSP-2191M

MSEL1 (PF1)

MSEL2 (PF2)

MSEL3 (PF3)

MSEL4 (PF4)

RESET

SOURCE

MSEL5 (PF5)

MSEL6 (PF6)

DF (PF7)

BYPASS

RESET

THE PULL-UP/PULL-DOWN

RESISTORS ON THE MSEL,

DF, AND BYPASS PINS

SELECT THE CORE CLOCK

RATIO.

HERE, THE SELECTION (6:1)

AND 25MHz INPUT CLOCK

PRODUCE A 150MHz CORE

CLOCK.

Figure 3. External Crystal Connections

The RESET input contains some hysteresis. If using an RC

circuit to generate your RESET signal, the circuit should use an

external Schmidt trigger.

The master reset sets all internal stack pointers to the empty stack

condition, masks all interrupts, and resets all registers to their

default values (where applicable). When RESET is released, if

there is no pending bus request and the chip is configured for

booting, the boot-loading sequence is performed. Program

control jumps to the location of the on-chip boot ROM

(0xFF 0000).

Power Supplies

The ADSP-2191M has separate power supply connections for

the internal (VDDINT) and external (VDDEXT) power supplies.

The internal supply must meet the 2.5 V requirement. The

external supply must be connected to a 3.3 V supply. All external

supply pins must be connected to the same supply.

Powerup Sequence

Power up together the two supplies VDDEXT and VDDINT. If

they cannot be powered up together, power up the internal (core)

supply first (powering up the core supply first reduces the risk of

latchup events.

Booting Modes

The ADSP-2191M has five mechanisms (listed in Table 6) for

automatically loading internal program memory after reset. Two

No-boot modes are also supported.

REV. 0

–11–

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