10XS3535(2011) データシートの表示（PDF） - Freescale Semiconductor

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10XS3535
(Rev.:2011)

Smart Front Corner Light Switch (Triple 10 mΩ and Dual 35 mΩ)

Freescale Semiconductor 

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

IGNITION INPUT (IGN)

The ignition input wakes the device. It also controls the Fail

mode activation. The signal is “high active”, meaning the

component is active in case of a logic high at the input.

FLASHER INPUT (FLASHER)

The flasher input wakes the device. It also controls the Fail

Mode activation. The signal is “high active”, meaning the

component is active in case of a logic high at the input.

FOG INPUT (FOG)

The fog input wakes the device. It also controls the Fail

Mode activation. The signal is “high active”, meaning the

component is active in case of a logic high at the input.

RESET INPUT (RST)

This input wakes the device when the RST pin is at

logic [1]. It is also used to initialize the device configuration

and the SPI faults registers when the signal is low. All SI/SO

registers described Table 7 and Table 10 are reset. The fault

management is not affected by RST.

CURRENT SENSE OUTPUT (CSNS)

The current sense output pin is an analog current output or

a voltage proportional to the temperature on the GND flag.

The routing to the external resistor is SPI programmable.

This current sense monitoring may be synchronized in

case of the OUT6 is not used. So, the current sense

monitoring can be synchronized with a rising edge on the

FETOUT pin (tCSNS(SYNC)) if CSNS sync SPI bit is set to logic

[1]. Connection of the FETOUT-pin to a MCU input pin allows

the MCU to sample the CSNS-pin during a valid time-slot.

Since this falling edge is generated at the end of this time-

slot, upon a switch-off command, this feature may be used to

implement maximum current control.

CHARGE PUMP (CP)

An external capacitor is connected between this pin and

the VBAT pin. It is used as a tank for the internal charge

pump. Its value is 100 nF ± 20%, 25 V maximum.

FETOUT OUTPUT (FETOUT)

This output pin is used to control an external MOSFET

(OUT6).

The high level of the FETOUT Output is VCC, if VBAT and

VCC are available, in case FETOUT is a controlled ON.

FETOUT is not protected if there is a short-circuit or under-

voltage on VBAT.

In case of a reverse battery, OUT6 is OFF.

FETIN INPUT (FETIN)

This input pin gives the current recopy of the external

MOSFET. It can be routed on CSNS output by a SPI

command.

SPI PROTOCOL DESCRIPTION

The SPI interface has a full-duplex, three-wire,

synchronous data transfer with four I/O lines associated with

it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO),

and Chip Select (CS).

The SI/SO pins of the 10XS3535 device follow a first-in,

first-out (D15 to D0) protocol, with both input and output

words transferring the most significant bit (MSB) first. All

inputs are compatible with 3.3 V and 5.0 V CMOS logic

levels, supplied by VCC.

The SPI lines perform the following functions:

SERIAL CLOCK (SCLK)

The SCLK pin clocks the internal shift registers of the

10XS3535 device. The SI pin accepts data into the input shift

register on the falling edge of the SCLK signal, while the SO

pin shifts data information out of the SO line driver on the

rising edge of the SCLK signal. It is important that the SCLK

pin be in a logic low state whenever CS makes any transition.

For this reason, it is recommended the SCLK pin be in a logic

[0] whenever the device is not accessed (CS logic [1] state).

SCLK has a passive pull-down, RDWN. When CS is logic [1],

signals at the SCLK and SI pins are ignored and SO is tri-

stated (high-impedance) (see Figure 8).

10XS353

20

Analog Integrated Circuit Device Data

Freescale Semiconductor

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