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ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
CS
High logic level
Low logic level
VOUT[1:5]
VPWR
Time
RPWM
50%VPWR
Time
VOUT[1:5]
70% VPWR
30% VPWR
t DLY(ON)
SR R
t DLY(OFF)
SR F
Figure 6. Output Slew Rate and Time Delays
Time
CS
High logic level
Low logic level
IOUT[1:5]
IMAX
Time
ICSNS
t DLY(ON)
t CSNS(VAL)
t CSNS(SET)
Time
t DLY(OFF)
VFETOUT
High logic level
Low logic level
t CSNS(SYNC)
Figure 7. Current Sensing Time Delays
Time
with CSNS sync bit = 1
Time
10XS353
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Analog Integrated Circuit Device Data
Freescale Semiconductor