ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 3.0V ≤ VCC ≤ 5.5V, 7.0V ≤ VBAT ≤ 20V, - 40°C ≤ TA ≤ 125°C, GND = 0V, unless
otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions, unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI INTERFACE CHARACTERISTICS
Maximum Frequency of SPI Operation
Rising Edge of CS to Falling Edge of CS (Required Setup Time)(46)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)(46)
Required High State Duration of SCLK (Required Setup Time)(46)
Required Low State Duration of SCLK (Required Setup Time)(46)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)(46)
SI to Falling Edge of SCLK (Required Setup Time)(47)
Falling Edge of SCLK to SI (Required Setup Time)(47)
SO Rise Time
CL = 80 pF
f SPI
–
t CS
–
t LEAD
–
t WSCLKH
–
t WSCLKL
–
t LAG
–
t SI(SU
–
t SI HOLD
–
t RSO
–
–
3.0
MHz
–
1.0
us
–
500
ns
–
167
ns
–
167
ns
50
167
ns
25
83
ns
25
83
ns
ns
25
50
SO Fall Time
CL = 80 pF
t FSO
ns
–
25
50
SI, CS, SCLK, Incoming Signal Rise Time(47)
SI, CS, SCLK, Incoming Signal Fall Time(47)
Time from Falling Edge of SCLK to SO Low-impedance(48)
Time from Rising Edge of SCLK to SO High-impedance(49)
t RSI
–
t FSI
–
t SO(EN)
–
t SO(DIS)
–
–
50
ns
–
50
ns
–
145
ns
65
145
ns
Notes
46. Maximum setup time required for the 10XS3535 is the minimum guaranteed time needed from the microcontroller.
47. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
48. Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CS.
49. Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CS.
10XS353
16
Analog Integrated Circuit Device Data
Freescale Semiconductor