54HCT163 データシートの表示（PDF） - Unspecified
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54HCT163 Datasheet PDF : 9 Pages
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High Speed CMOS TTL Input – 74HCT163
Timing Requirements6
PARAMETER
SYMBOL
VCC
Minimum Setup Time,
Pn to CP
Minimum Setup Time,
SPE to CP
Minimum Setup Time,
MR to CP
Minimum Setup Time,
TE or PE to CP
Minimum Hold Time,
CP to Pn
Minimum Hold Time,
CP to SPE
Minimum Hold Time,
CP to MR
Minimum Hold Time,
CP to TE or PE
Minimum Recovery
Time, SPE Inactive to
CP
tSU
5V ±10%
th
5V ±10%
trec
5V ±10%
Minimum Pulse Width,
CP
tw
5V ±10%
Maximum Input Rise
and Fall times
tr, tf
5V ±10%
CONDITIONS
CL = 50pF,
Input
tr = tf = 6ns
CL = 50pF,
Input
tr = tf = 6ns
CL = 50pF,
Input
tr = tf = 6ns
CL = 50pF,
Input
tr = tf = 6ns
CL = 50pF,
Input
tr = tf = 6ns
25°C
12
12
12
12
3
3
3
3
12
12
500
Rev 1.0
06/06/19
LIMITS
UNITS
85°C FULL RANGE5
18
18
ns
18
18
ns
18
18
ns
18
18
ns
3
3
3
3
ns
3
3
3
3
17
17
ns
15
15
ns
500
500
ns
Switching Waveforms
Figure 1 – Propagation Delay & Clock Timing,
Clock to Output
Figure 2 – Propagation Delay & Recovery Time,
Reset to Clock
Page 6 of 9
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