DS21448 データシートの表示（PDF） - Maxim Integrated

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DS21448

3.3V E1/T1/J1 Quad Line Interface

Maxim Integrated 

DS21448 3.3V T1/E1/J1 Quad Line Interface

LIST OF TABLES

Table 2-A. Bus Interface Selection ............................................................................................................. 7

Table 2-B. Pin Assignments ....................................................................................................................... 7

Table 2-C. Parallel Interface Mode Pin Description.................................................................................... 9

Table 2-D. Serial Interface Mode Pin Description .................................................................................... 10

Table 2-E. Hardware Interface Mode Pin Description .............................................................................. 11

Table 3-A. DS21448 vs. DS21Q348 Pin Differences ............................................................................... 13

Table 4-A. Loopback Control in Hardware Mode ..................................................................................... 14

Table 4-B. Transmit Data Control in Hardware Mode............................................................................... 14

Table 4-C. Receive Sensitivity Settings in Hardware Mode ..................................................................... 14

Table 4-D. Monitor Gain Settings in Hardware Mode ............................................................................... 14

Table 4-E. Internal Rx Termination Select in Hardware Mode ................................................................. 14

Table 4-F. MCLK Selection in Hardware Mode ........................................................................................ 15

Table 4-G. Parallel Port Mode Selection .................................................................................................. 18

Table 4-H. Register Map .......................................................................................................................... 18

Table 4-I. Receive Sensitivity Settings ..................................................................................................... 22

Table 4-J. Backplane Clock Select........................................................................................................... 22

Table 4-K. Monitor Gain Settings ............................................................................................................. 22

Table 4-L. Internal Rx Termination Select ................................................................................................ 22

Table 5-A. Received Alarm Criteria .......................................................................................................... 25

Table 5-B. Receive Level Indication ......................................................................................................... 27

Table 6-A. Transmit Code Length ............................................................................................................ 29

Table 6-B. Receive Code Length ............................................................................................................. 29

Table 6-C. Definition of Received Errors .................................................................................................. 32

Table 6-D. Function of ECRS Bits and RNEG Pin.................................................................................... 32

Table 7-A. Line Build-Out Select for E1 in Register CCR4 (ETS = 0) ...................................................... 34

Table 7-B. Line Build-Out Select for T1 in Register CCR4 (ETS = 1) ...................................................... 34

Table 7-C. Line Build-Out Select for E1 in Register CCR4 (ETS = 0) Using Alternate Transformer

Configuration...................................................................................................................................... 35

Table 7-D. Transformer Specifications (3.3V Operation).......................................................................... 35

Table 8-A. Instruction Codes for IEEE 1149.1 Architecture ..................................................................... 45

Table 8-B. ID Code Structure ................................................................................................................... 46

Table 8-C. Device ID Codes..................................................................................................................... 46

Table 8-D. Boundary Scan Control Bits.................................................................................................... 47

Table 10-A. AC Characteristics—Multiplexed Parallel Port (BIS0 = 0)..................................................... 49

Table 10-B. AC Characteristics—Nonmultiplexed Parallel Port (BIS0 = 1) .............................................. 51

Table 10-C. AC Characteristics—Serial Port (BIS1 = 1, BIS0 = 0)........................................................... 53

Table 10-D. AC Characteristics—Receive Side ....................................................................................... 54

Table 10-E. AC Characteristics—Transmit Side ...................................................................................... 55

Table 13-A. Thermal Characteristics—BGA ............................................................................................. 60

Table 13-B. Theta-JA (θJA) vs. Airflow—BGA ........................................................................................... 60

Table 13-C. Thermal Characteristics—LQFP ........................................................................................... 60

Table 13-D. Theta-JA (θJA) vs. Airflow—LQFP ......................................................................................... 60

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