DS21448 データシートの表示（PDF） - Maxim Integrated
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DS21448 Datasheet PDF : 60 Pages
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DS21448 3.3V T1/E1/J1 Quad Line Interface
TABLE OF CONTENTS
1. BLOCK DIAGRAMS ........................................................................................................................ 5
2. PIN DESCRIPTION .......................................................................................................................... 7
3. DETAILED DESCRIPTION ............................................................................................................ 13
3.1 DS21448 AND DS21Q348 DIFFERENCES...................................................................................... 13
4. PORT OPERATION ....................................................................................................................... 14
4.1 HARDWARE MODE......................................................................................................................... 14
4.2 SERIAL PORT OPERATION.............................................................................................................. 15
4.3 PARALLEL PORT OPERATION ......................................................................................................... 18
4.3.1 Device Power-Up and Reset................................................................................................................ 18
4.3.2 Register Map........................................................................................................................................ 18
4.3.3 Control Registers ................................................................................................................................. 19
5. STATUS REGISTERS.................................................................................................................... 23
6. DIAGNOSTICS .............................................................................................................................. 28
6.1 IN-BAND LOOP-CODE GENERATION AND DETECTION ...................................................................... 28
6.2 LOOPBACKS .................................................................................................................................. 31
6.2.1 Remote Loopback (RLB) ..................................................................................................................... 31
6.2.2 Local Loopback (LLB) .......................................................................................................................... 31
6.2.3 Analog Loopback (LLB) ....................................................................................................................... 31
6.2.4 Dual Loopback (DLB)........................................................................................................................... 31
6.3 PRBS GENERATION AND DETECTION ............................................................................................ 31
6.4 ERROR COUNTER.......................................................................................................................... 31
6.5 ERROR COUNTER UPDATE ............................................................................................................ 32
6.6 ERROR INSERTION ........................................................................................................................ 32
7. ANALOG INTERFACE................................................................................................................... 33
7.1 RECEIVER ..................................................................................................................................... 33
7.2 TRANSMITTER ...............................................................................................................................33
7.3 JITTER ATTENUATOR ..................................................................................................................... 34
7.4 G.703 SYNCHRONIZATION SIGNAL................................................................................................. 34
8. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .................................. 43
8.1 JTAG TAP CONTROLLER STATE MACHINE .................................................................................... 43
8.2 INSTRUCTION REGISTER ................................................................................................................ 45
8.3 TEST REGISTERS .......................................................................................................................... 46
9. OPERATING PARAMETERS ........................................................................................................ 48
10. AC TIMING PARAMETERS AND DIAGRAMS.............................................................................. 49
11. PIN CONFIGURATIONS ................................................................................................................ 56
11.1 144-PIN BGA ............................................................................................................................56
11.2 128-PIN LQFP...........................................................................................................................57
12. PACKAGE INFORMATION ........................................................................................................... 58
12.1 144-BALL TE-PBGA (56-G6020-001) ....................................................................................... 58
12.2 128-PIN LQFP (56-G4011-001) ................................................................................................ 59
13. THERMAL INFORMATION ............................................................................................................60
14. REVISION HISTORY...................................................................................................................... 60
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