DS21448 データシートの表示（PDF） - Maxim Integrated
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DS21448 Datasheet PDF : 60 Pages
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DS21448 3.3V T1/E1/J1 Quad Line Interface
PIN
RCLK1–RCLK4
TPOS1–TPOS4
TNEG1–TNEG4
TCLK1–TCLK4
JTRST
JTMS
JTCLK
JTDI
JTDO
VSM
TVDD1–TVDD4
VDD1–VDD4
TVSS1–TVSS4
VSS1–VSS4
I/O
FUNCTION
O
Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in absence of
signal at RTIP and RRING.
I
Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0) or the rising edge
(CCR2.1 = 1) of TCLK for data to be transmitted out onto the line.
I
Transmit Negative Data. Sampled on the falling edge (CCR2.1 = 0) or the rising edge
(CCR2.1 = 1) of TCLK for data to be transmitted out onto the line.
Transmit Clock. A 2.048MHz or 1.544MHz primary clock. It is used to clock data through the
I transmit-side formatter. It can be sourced internally by MCLK or RCLK. See Common Control
Register 1 and Figure 1-3.
I JTAG Reset
I JTAG Mode Select
I JTAG Clock
I JTAG Data In
O JTAG Data Out
I Voltage Supply Mode (LQFP only). Should be wired low for correct operation.
— 3.3V, ±5% Transmitter Positive Supply
— 3.3V, ±5% Positive Supply
— Transmitter Signal Ground
— Signal Ground
Table 2-D. Serial Interface Mode Pin Description
PIN
INT
TXDIS/TEST
HRST
I/O
FUNCTION
I/O
Interrupt (INT). Flags host controller during conditions and change of conditions defined in the
status register. Active-low, open-drain output.
Tri-State Control, Multifunctional. Set this pin high with all CS1–CS4 inputs inactive to tri-state
I TTIP1–TTIP4 and TRING1–TRING4. Set this pin high with any of the CS1–CS4 inputs active to
tri-state all outputs and I/O pins (including the parallel control port). Set low for normal operation.
I
Hardware Reset. Bringing HRST low resets the DS21448, setting all control bits to the all-zeros
default state.
MCLK
Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This
I clock is used internally for both clock/data recovery and for jitter attenuation. A T1 1.544MHz
clock source is optional (Note 1).
BIS0/BIS1
I Bus Interface Select Bit 0 and 1. Used to select bus interface option. See Table 2-A for details.
CS1
I
Chip Select 1. Must be low to read or write to channel 1 of the device. CS1 is an active-low
signal.
CS2
I
Chip Select 2. Must be low to read or write to channel 2 of the device. CS2 is an active-low
signal.
CS3
I
Chip Select 3. Must be low to read or write to channel 3 of the device. CS3 is an active-low
signal.
CS4
I
Chip Select 4. Must be low to read or write to channel 4 of the device. CS4 is an active-low
signal.
ICES
I
Input Clock-Edge Select. Selects whether the serial interface data input (SDI) is sampled on the
rising (ICES = 0) or falling edge (ICES = 1) of SCLK.
OCES
I
Output Clock-Edge Select. Selects whether the serial interface data output (SDO) changes on
the rising (OCES = 1) or falling edge (OCES = 0) of SCLK.
SCLK
I Serial Clock. Serial interface clock.
SDI
I Serial Data Input. Serial interface data input.
SDO
PBEO1–PBEO4
O Serial Data Output. Serial interface data output.
PRBS Bit-Error Output. The receiver constantly searches for a 215 - 1 (E1) or a QRSS (T1)
PRBS, depending on the ETS bit setting (CCR1.7). It remains high if it is out of synchronization
O
with the PRBS pattern. It goes low when synchronized to the PRBS pattern. Any errors in the
received pattern after synchronization cause a positive-going pulse (with same period as E1 or
T1 clock) synchronous with RCLK. PRBS bit errors can also be reported to the ECR1 and ECR2
registers by setting CCR6.2 to logic 1.
RCL1/LOTC1–
RCL4/LOTC4
Receive Carrier Loss/Loss-of-Transmit Clock. An output that toggles high during a receive carrier
O loss (CCR2.7 = 0) or toggles high if the TCLK pin has not been toggled for 5µs ± 2µs
(CCR2.7 = 1). CCR2.7 defaults to logic 0 when in hardware mode.
RTIP1–RTIP4
RRING1–RRING4
I
Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect through a
1:1 transformer to the line. See Section 7 for details.
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