ADSP-2191MKCA-160X データシートの表示（PDF） - Analog Devices

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ADSP-2191MKCA-160X

DSP Microcomputer

Analog Devices 

35(/,0,1$5< 7(&+1,&$/ '$7$

September 2001 For current information contact Analog Devices at 800/262-5643

ADSP-2191

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Figure 6. JTAG Target Board Connector for JTAG

Equipped Analog Devices DSP (Jumpers in

Place)

As can be seen in Figure 6, there are two sets of signals on

the header. There are the standard JTAG signals TMS,

TCK, TDI, TDO, TRST, and EMU used for emulation

purposes (via an emulator). There are also secondary JTAG

signals BTMS, BTCK, BTDI, and BTRST that are option-

ally used for board-level (boundary scan) testing.

When the emulator is not connected to this header, place

jumpers across BTMS, BTCK, BTRST, and BTDI as

shown in Figure 7. This holds the JTAG signals in the

correct state to allow the DSP to run free. Remove all the

jumpers when connecting the emulator to the JTAG header.

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Figure 7. JTAG Target Board Connector with No Local

Boundary Scan

JTAG Emulator Pod Connector

Figure 8 details the dimensions of the JTAG pod connector

at the 14-pin target end. Figure 9 displays the keep-out area

for a target board header. The keep-out area allows the pod

connector to properly seat onto the target board header.

This board area should contain no components (chips,

resistors, capacitors, etc.). The dimensions are referenced

to the center of the 0.25" square post pin.







Figure 8. JTAG Pod Connector Dimensions





Figure 9. JTAG Pod Connector Keep-Out Area

Design-for-Emulation Circuit Information

For details on target board design issues including: single

processor connections, multiprocessor scan chains, signal

buffering, signal termination, and emulator pod logic, see

the EE-68: Analog Devices JTAG Emulation Technical

Reference on the Analog Devices website (www.ana-

log.com)—use site search on “EE-68”. This document is

updated regularly to keep pace with improvements to

emulator support.

Additional Information

This data sheet provides a general overview of the

ADSP-2191 architecture and functionality. For detailed

information on the ADSP-219x family core architecture

and instruction set, refer to the ADSP-219x/2191 DSP

Hardware Reference.

PIN DESCRIPTIONS

ADSP-2191 pin definitions are listed in Table 7. All

ADSP-2191 inputs are asynchronous and can be asserted

asynchronously to CLKIN (or to TCK for TRST).

Unused inputs should be tied or pulled to VDDEXT or GND,

except for ADDR21–0, DATA15–0, PF7-0, and inputs that

have internal pull-up or pull-down resistors (TRST,

BMODE0, BMODE1, OPMODE, BYPASS, TCK, TMS,

REV. PrC

This information applies to a product under development. Its characteristics and specifications are subject to change with-

17

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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