ADSP-2191MKCA-160X データシートの表示（PDF） - Analog Devices

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ADSP-2191MKCA-160X

DSP Microcomputer

Analog Devices 

35(/,0,1$5< 7(&+1,&$/ '$7$

September 2001 For current information contact Analog Devices at 800/262-5643

ADSP-2191

ROM memory space and uses the top 16 locations of

Page 0 program memory and the top 272 locations of

Page 0 data memory.

The internal boot ROM sets semaphore A (an IO register

within the host port) and then polls until the semaphore

is reset. Once detected, the internal boot ROM will remap

the interrupt vector table to Page 0 internal memory and

jump to address 0x0000 internal. From the point of view

of the host interface, an external host has full control of

the DSP's memory map. The Host has the freedom to

directly write internal memory, external memory, and

internal I/O memory space. The DSP core execution is

held off until the Host clears the semaphore register. This

strategy allows the maximum flexibility for the Host to

boot in the program and data code, by leaving it up to

the programmer.

• Execute from memory external 8 bits (No Boot)—

execution starts from Page 1 of external memory space,

packing either 8- or 16-bit external data into 24-bit

internal data. The External Port Interface is configured

for the default clock multiplier (128) and read waitstates

(7).

• Boot from UART—The Host downloads

boot-stream-formatted program using an autobaud

handshake sequence. The Host agent selects a baud rate

within the UART’s clocking capabilities. After a hardware

reset, the DSP’s UART transmits 0xFF values (eight bits

data, one start bit, one stop bit, no parity bit) until

detecting the start of the first memory block. The UART

boot routine is located in internal ROM memory space

and uses the top 16 locations of Page 0 program memory

and the top 272 locations of Page 0 data memory.

• Boot from SPI, up to 4K bits—The SPI0 port uses the

SPI0SEL1 (reconfigured PF2) output pin to select a

single serial EPROM device, submits a read command at

address 0x00, and begins clocking consecutive data into

internal or external memory. Use only SPI-compatible

EPROMs of ≤ 4K bit (12-bit address range). The SPI0

boot routine located in internal ROM memory space

executes a boot-stream-formatted program, using the top

16 locations of Page 0 program memory and the top 272

locations of Page 0 data memory. The SPI boot configu-

ration is SPIBAUD0=60 (decimal), CPHA=1, CPOL=1,

8-bit data, and MSB first.

• Boot from SPI, from >4K bits to 512K bits—The SPI0

port uses the SPI0SEL1 (re-configured PF2) output pin

to select a single serial EPROM device, submits a read

command at address 0x00, and begins clocking consecu-

tive data into internal or external memory. Use only

SPI-compatible EPROMs of ≥ 4K bit (16-bit address

range). The SPI0 boot routine located in internal ROM

memory space executes a boot-stream-formatted

program, using the top 16 locations of Page 0 program

memory and the top 272 locations of Page 0 data memory.

Bus Request and Bus Grant

The ADSP-2191 can relinquish control of the data and

address buses to an external device. When the external

device requires access to the bus, it asserts the bus request

(BR) signal. The (BR) signal is arbitrated with core and

peripheral requests. External Bus requests have the lowest

priority. If no other internal request is pending, the external

bus request will be granted. Due to synchronizer and arbi-

tration delays, bus grants will be provided with a minimum

of three peripheral clock delays. The ADSP-2191 will

respond to the bus grant by:

• Three-stating the data and address buses and the MS3–0,

BMS, IOMS, RD, and WR output drivers.

• Asserting the bus grant (BG) signal.

The ADSP-2191 will halt program execution if the bus is

granted to an external device and an instruction fetch or

data read/write request is made to external general-purpose

or peripheral memory spaces. If an instruction requires two

external memory read accesses, the bus will not be granted

between the two accesses. If an instruction requires an

external memory read and an external memory write access,

the bus may be granted between the two accesses. The

external memory interface can be configured so that the

core will have exclusive use of the interface. DMA and Bus

Requests will be granted. When the external device releases

BR, the DSP releases BG and continues program execution

from the point at which it stopped.

The bus request feature operates at all times, even while the

DSP is booting and RESET is active.

The ADSP-2191 asserts the BGH pin when it is ready to

start another external port access, but is held off because

the bus was previously granted. This mechanism can be

extended to define more complex arbitration protocols for

implementing more elaborate multimaster systems.

Instruction Set Description

The ADSP-2191 assembly language instruction set has an

algebraic syntax that was designed for ease of coding and

readability. The assembly language, which takes full

advantage of the processor’s unique architecture, offers the

following benefits:

• ADSP-219x assembly language syntax is a superset of and

source-code-compatible (except for two data registers

and DAG base address registers) with ADSP-218x family

syntax. It may be necessary to restructure ADSP-218x

programs to accommodate the ADSP-2191’s unified

memory space and to conform to its interrupt vector map.

• The algebraic syntax eliminates the need to remember

cryptic assembler mnemonics. For example, a typical

arithmetic add instruction, such as AR = AX0 + AY0,

resembles a simple equation.

• Every instruction, but two, assembles into a single, 24-bit

word that can execute in a single instruction cycle. The

exceptions are two dual word instructions. One writes 16-

REV. PrC

This information applies to a product under development. Its characteristics and specifications are subject to change with-

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out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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