ADSP-2191MKCA-160X データシートの表示（PDF） - Analog Devices

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ADSP-2191MKCA-160X

DSP Microcomputer

Analog Devices 

35(/,0,1$5< 7(&+1,&$/ '$7$

ADSP-2191

For current information contact Analog Devices at 800/262-5643

September 2001

include support for 5–8 data bits; 1 or 2 stop bits; and none,

even, or odd parity. The UART port supports two modes

of operation:

• PIO (programmed I/O)

The DSP’s core sends or receives data by writing or

reading I/O-mapped UATX or UARX registers, respec-

tively. The data is double-buffered on both transmit and

receive.

• DMA (direct memory access)

The DMA controller transfers both transmit and receive

data. This reduces the number and frequency of inter-

rupts required to transfer data to and from memory. The

UART has two dedicated DMA channels. These DMA

channels have lower priority than most DMA channels

because of their relatively low service rates.

The UART’s baud rate (see Figure 4), serial data format,

error code generation and status, and interrupts are

programmable:

• Supported bit rates range from 9.5 bits to 6.25M bits per

second (100 MHz peripheral clock).

• Supported data formats are 7- or 12-bit frames.

• Transmit and receive status can be configured to generate

maskable interrupts to the DSP’s core.

UART Clock Rate = H-1---6--C---×-L----D-K---

Figure 4. UART Clock Rate Calculation1

1Where D = 1 to 65536

The timers can be used to provide a hardware-assisted

autobaud detection mechanism for the UART interface.

Programmable Flag (PFx) Pins

The ADSP-2191 has 16 bidirectional, general-purpose I/O,

Programmable Flag (PF15–0) pins. The PF7–0 pins are

dedicated to general-purpose I/O. The PF15–8 pins serve

either as general-purpose I/O pins (if the DSP is connected

to an 8-bit external data bus) or serve as DATA15–8 lines

(if the DSP is connected to a 16-bit external data bus). The

Programmable Flag pins have special functions for clock

multiplier selection and for SPI port operation. For more

information, see Serial Peripheral Interface (SPI) Ports on

page 11 and Clock Signals on page 13. Ten mem-

ory-mapped registers control operation of the

Programmable Flag pins:

• Flag Direction register

Specifies the direction of each individual PFx pin as input

or output.

• Flag Control and Status registers

Specify the value to drive on each individual PFx output

pin. As input, software can predicate instruction

execution on the value of individual PFx input pins

captured in this register. One register sets bits, and one

register clears bits.

• Flag Interrupt Mask registers

Enable and disable each individual PFx pin to function

as an interrupt to the DSP’s core. One register sets bits to

enable interrupt function, and one register clears bits to

disable interrupt function. Input PFx pins function as

hardware interrupts, and output PFx pins function as

software interrupts—latching in the IMASK and IRPTL

registers.

• Flag Interrupt Polarity register

Specifies the polarity (active high or low) for interrupt

sensitivity on each individual PFx pin.

• Flag Sensitivity registers

Specify whether individual PFx pins are level- or

edge-sensitive and specify—if edge-sensitive—whether

just the rising edge or both the rising and falling edges of

the signal are significant. One register selects the type of

sensitivity, and one register selects which edges are signif-

icant for edge-sensitivity.

Low Power Operation

The ADSP-2191 has four low-power options that signifi-

cantly reduce the power dissipation when the device

operates under standby conditions. To enter any of these

modes, the DSP executes an IDLE instruction. The

ADSP-2191 uses configuration of the PDWN, STOPCK,

and STOPALL bits in the PLLCTL register to select

between the low-power modes as the DSP executes the

IDLE. Depending on the mode, an IDLE shuts off clocks

to different parts of the DSP in the different modes. The

low power modes are:

• Idle

• Power-Down Core

• Power-Down Core/Peripherals

• Power-Down All

Idle Mode

When the ADSP-2191 is in Idle mode, the DSP core stops

executing instructions, retains the contents of the instruc-

tion pipeline, and waits for an interrupt. The core clock and

peripheral clock continue running.

12

This information applies to a product under development. Its characteristics and specifications are subject to change with-

REV. PrC

out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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