ADSP-2191MKCA-160X データシートの表示（PDF） - Analog Devices
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ADSP-2191MKCA-160X Datasheet PDF : 66 Pages
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ADSP-2191
For current information contact Analog Devices at 800/262-5643
September 2001
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As indicated in Table 6, the OPMODE pin has a dual role,
acting as a boot mode select during reset and determining
SPORT or SPI operation at runtime. If the OPMODE pin
at reset is the opposite of what is needed in an application
during runtime, the application needs to set the OPMODE
bit appropriately during runtime prior to using the corre-
sponding peripheral.
Booting Modes
The ADSP-2191 has seven mechanisms (listed in Table 6)
for automatically loading internal program memory
after reset.
Table 6. Select Boot Mode (OPMODE, BMODE1, and
BMODE0)
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Figure 5. External Crystal Connections
The power-up sequence is defined as the total time required
for the crystal oscillator circuit to stabilize after a valid VDD
is applied to the processor, and for the internal phase-locked
loop (PLL) to lock onto the specific crystal frequency. A
minimum of 100 µs ensures that the PLL has locked, but
does not include the crystal oscillator start-up time. During
this power-up sequence the RESET signal should be held
low. On any subsequent resets, the RESET signal must meet
the minimum pulsewidth specification, tRSP.
The RESET input contains some hysteresis. If using an RC
circuit to generate your RESET signal, the circuit should
use an external Schmidt trigger.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts, and resets all registers
to their default values (where applicable). When RESET is
released, if there is no pending bus request and the chip is
configured for booting, the boot-loading sequence is per-
formed. Program control jumps to the location of the
on-chip boot ROM (0xFF0000).
Power Supplies
The ADSP-2191 has separate power supply connections for
the internal (VDDINT) and external (VDDEXT) power supplies.
The internal supply must meet the 2.5 V requirement. The
external supply must be connected to a 3.3 V supply. All
external supply pins must be connected to the same supply.
Function
0 0 0 Execute from external memory 16 bits
(No Boot)
0 0 1 Boot from EPROM
0 1 0 Boot from Host
0 1 1 Reserved
1 0 0 Execute from external memory 8 bits
(No Boot)
1 0 1 Boot from UART
1 1 0 Boot from SPI, up to 4K bits
1 1 1 Boot from SPI, >4K bits up to
512K bits
The OPMODE, BMODE1, and BMODE0 pins, sampled
during hardware reset, and three bits in the Reset Configu-
ration Register implement these modes:
• Boot from memory external 16 bits—The memory boot
routine located in boot ROM memory space executes a
boot-stream-formatted program located at address
0x10000 of boot memory space, packing 16-bit external
data into 24-bit internal data. The External Port Interface
is configured for the default clock multiplier (128) and
read waitstates (7).
• Boot from EPROM—The EPROM boot routine located
in boot ROM memory space executes a boot-stream-for-
matted program located at address 0x10000 of boot
memory space, packing 8- or 16-bit external data into
24-bit internal data. The External Port Interface is con-
figured for the default clock multiplier (32) and read
waitstates (7).
• Boot from Host—The (8- or 16-bit) Host downloads a
boot-stream-formatted program to internal or external
memory. The Host’s boot routine is located in internal
14
This information applies to a product under development. Its characteristics and specifications are subject to change with-
REV. PrC
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
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