CY7C4282V(2003) データシートの表示（PDF） - Cypress Semiconductor

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CY7C4282V
(Rev.:2003)

64K/128K x 9 Low-Voltage Deep Sync FIFOs with Retransmit and Depth Expansion

Cypress Semiconductor 

Depth Expansion Configuration

The CY7C4282V/92V can easily be adapted to applications

requiring more than 64K/128K words of buffering. Figure 3

shows Depth Expansion using three CY7C4282V/92Vs.

Maximum depth is limited only by signal loading. Follow these

steps:

1. The first device must be designated by grounding the First

Load (FL) control input.

2. All other devices must have FL in the HIGH state.

3. The Expansion Out (XO) pin of each device must be tied to

the Expansion In (XI) pin of the next device.

4. EF and FF composite flags are created by ORing together

each individual respective flag.

XO

WCLK RCLK

WEN

REN

RS

OE

7C4282V

D 7C4292V Q

VCC

FL

FF

EF

XI

CY7C4282V

CY7C4292V

DATAIN (D)

XO

WCLK

RCLK

WEN

REN

RS

OE

7C4282V

D 7C4292V Q

VCC

FL

FF

EF

XI

DATA OUT (Q)

WRITECLOCK (WCLK)

WRITEENABLE (WEN)

RESET (RS)

XO

WCLK RCLK

WEN

REN

RS 7C4282V OE

D 7C4292V Q

READ CLOCK (RCLK)

READ ENABLE (REN)

OUTPUTENABLE (OE)

FF

FF

EF

EF

FL XI

FIRST LOAD (FL)

Figure 3. Block Diagram of 64Kx9/128Kx9 Low-Voltage Deep Sync FIFO Memory

with Programmable Flags used in Depth Expansion Configuration

Document #: 38-06014 Rev. *B

Page 6 of 15

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