CY7C4282V(2003) データシートの表示（PDF） - Cypress Semiconductor

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CY7C4282V
(Rev.:2003)

64K/128K x 9 Low-Voltage Deep Sync FIFOs with Retransmit and Depth Expansion

Cypress Semiconductor 

CY7C4282V

CY7C4292V

Pin Definitions (continued)

FF

Full Flag

PAE

PAF/XO

FL/RT

Programmable

Almost Empty

Programmable

Almost Full/

Expansion

Output

First Load/

Retransmit

XI/LD

Expansion

Input/Load

OE

Output Enable

RS

Reset

O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.

O When PAE is LOW, the FIFO is almost empty based on the almost empty offset value

programmed into the FIFO. PAE is synchronized to RCLK.

O Dual-Mode Pin. Cascaded – Connected to XI of next device. Not Cascaded – When

PAF is LOW, the FIFO is almost full based on the almost full offset value programmed into the

FIFO. PAF is synchronized to WCLK.

I Dual-Mode Pin. Cascaded – The first device in the daisy chain will have FL tied to VSS;

all other devices will have FL tied to VCC. In standard mode or width expansion, FL

is tied to VSS on all devices. Not Cascaded – Retransmit function is available in

stand-alone mode by strobing RT.

I Dual-Mode Pin. Cascaded – Connected to XO of previous device. Not Cascaded –

LD is used to write or read the programmable flag offset registers. LD must be asserted

LOW during reset to enable standalone or width expansion operation. If programmable

offset register access is not required, LD can be tied to RS directly.

I When OE is LOW, the FIFO’s data outputs drive the bus to which they are

connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.

I Resets device to empty condition. A reset is required before an initial read or write

operation after power-up.

Functional Description (continued)

The CY7C4282V/92V provides four status pins: Empty, Full,

Programmable Almost Empty, and Programmable Almost Full.

The Almost Empty/Almost Full flags are programmable to

single word granularity. The programmable flags default to

Empty+7 and Full-7.

The flags are synchronous, i.e., they change state relative to

either the read clock (RCLK) or the write clock (WCLK). When

entering or exiting the Empty and Almost Empty states, the

flags are updated exclusively by the RCLK. The flags denoting

Almost Full, and Full states are updated exclusively by WCLK.

The synchronous flag architecture guarantees that the flags

maintain their status for at least one cycle

All configurations are fabricated using an advanced 0.35m

CMOS technology. Input ESD protection is greater than

2001V, and latch-up is prevented by the use of guard rings.

Architecture

The CY7C4282V/92V consists of an array of 64K to 128K

words of 9 bits each (implemented by a dual-port array of

SRAM cells), a read pointer, a write pointer, control signals

(RCLK, WCLK, REN, WEN, RS), and flags (EF, PAE, PAF, FF).

Resetting the FIFO

Upon power-up, the FIFO must be reset with a Reset (RS)

cycle. This causes the FIFO to enter the Empty condition

signified by EF being LOW. All data outputs (Q0 - 8) go LOW

tRSF after the rising edge of RS. In order for the FIFO to reset

to its default state, the user must not read or write while RS is

LOW. All flags are guaranteed to be valid tRSF after RS is taken

LOW.

During reset of the FIFO, the state of the XI/LD pin determines

if depth expansion operation is used. For depth expansion

operation, XI/LD is tied to XO of the next device. See “Depth-

Expansion Configuration” and Figure 3. For standalone or

width expansion configuration, the XI/LD pin must be asserted

LOW during reset.

There is a 0-ns hold time requirement for the XI/LD configu-

ration at the RS deassertion edge. This allows the user to tie

XI/LD to RS directly for applications that do not require access

to the flag offset registers.

FIFO Operation

When the WEN is asserted LOW and FF is HIGH, data present

on the D0-8 pins is written into the FIFO on each rising edge

of the WCLK signal. Similarly, when the REN is asserted LOW

and EF is HIGH, data in the FIFO memory will be presented

on the Q0-8 outputs. New data will be presented on each rising

edge of RCLK while REN is active. REN must set up tENS

before RCLK for it to be a valid read function. WEN must occur

tENS before WCLK for it to be a valid write function.

An Output Enable (OE) pin is provided to three-state the Q0-8

outputs when OE is asserted. When OE is enabled (LOW),

data in the output register will be available to the Q0-8 outputs

after tOE. If devices are cascaded, the OE function will only

output data on the FIFO that is read enabled.

The FIFO contains overflow circuitry to disallow additional

writes when the FIFO is full, and underflow circuitry to disallow

additional reads when the FIFO is empty. An empty FIFO

maintains the data of the last valid read on its Q0-8 outputs

even after additional reads occur.

Programming

When LD is held LOW during Reset, this pin is the Load

Enable (LD) for flag offset programming. In this configuration,

LD can be used to access the four 9-bit offset registers

contained in the CY7C4282V/92V for writing or reading data

to these registers.

When the device is configured for programmable flags and

both LD and WEN are LOW, the first LOW-to-HIGH transition

of WCLK writes data from the data inputs to the empty offset

least significant bit (LSB) register. The second, third, and

fourth LOW-to-HIGH transitions of WCLK store data in the

empty offset most significant bit (MSB) register, full offset LSB

register, and full offset MSB register, respectively, when LD

Document #: 38-06014 Rev. *B

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