CY7C4282V(2003) データシートの表示（PDF） - Cypress Semiconductor
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CY7C4282V
(Rev.:2003)
(Rev.:2003)
Cypress Semiconductor
CY7C4282V Datasheet PDF : 15 Pages
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Pin Configuration
STQFP
Top View
WEN
1
RS
2
D8
D7
3
4
D6
5
N/C
6
N/C
7
N/C
8
N/C
9
N/C
10
N/C
11
N/C
12
D5
D4
D3
D2
13
14
15
16
CY7C4282V
CY7C4292V
48
Q5
47
Q4
46
GND
45
Q3
44
Q2
43
VCC
42
Q1
41
Q0
40
GND
39
N/C
38
FF
37
EF
36
OE
35
GND
34
FL/RT
33
N/C
CY7C4282V
CY7C4292V
Selection Guide
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
Active Power Supply Current (ICC) Commercial
Industrial
7C4282V/92V-10
100
8
10
3.5
0
8
25
7C4282V/92V-15
66.7
10
15
4
0
10
25
30
7C4282V/92V-25
40
15
25
6
1
15
25
Unit
MHz
ns
ns
ns
ns
ns
mA
Density
Package
CY7C4282V
64k × 9
64-pin 10 × 10 TQFP
CY7C4292V
128k × 9
64-pin 10 × 10 TQFP
Pin Definitions
Signal Name Description
D0−8
Q0−8
WEN
Data Inputs
Data Outputs
Write Enable
REN
Read Enable
WCLK
Write Clock
RCLK
Read Clock
EF
Empty Flag
I/O
Description
I Data Inputs for 9-bit bus.
O Data Outputs for 9-bit bus.
I The only write enable when device is configured to have programmable flags. Data
is written on a LOW-to-HIGH transition of WCLK when WEN is asserted and FF is HIGH.
I Enables the device for Read operation. REN must be asserted LOW to allow a Read
operation.
I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
I The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is LOW, RCLK reads data out of the programmable flag-offset register.
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
Document #: 38-06014 Rev. *B
Page 2 of 15
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