CY7C4282V(2003) データシートの表示（PDF） - Cypress Semiconductor
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CY7C4282V
(Rev.:2003)
(Rev.:2003)
Cypress Semiconductor
CY7C4282V Datasheet PDF : 15 Pages
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CY7C4282V
CY7C4292V
Table 2. Status Flags
Number of Words in FIFO
CY7C4282V
CY7C4292V
0
1 to n[2]
0
1 to n[2]
(n + 1) to (65536 − (m + 1))
(65536 − m)[3] to 65535
(n + 1) to (131072 − (m + 1))
(131072 − m)[3] to 131071
65536
131072
FF
PAF
H
H
H
H
H
H
H
L
L
L
PAE
EF
L
L
L
H
H
H
H
H
H
H
Retransmit
Width-Expansion Configuration
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred and at least one word has been read
since the last RS cycle. A HIGH pulse on RT resets the internal
read pointer to the first physical location of the FIFO. WCLK
and RCLK may be free running but must be disabled during
and tRTR after the retransmit pulse. With every valid read cycle
after retransmit, previously accessed data is read and the read
pointer is incremented until it is equal to the write pointer. Flags
are governed by the relative locations of the read and write
pointers and are updated during a retransmit cycle. Data
written to the FIFO after activation of RT are transmitted also.
The full depth of the FIFO can be repeatedly retransmitted.
Word width may be increased simply by connecting the corre-
sponding input control signals of multiple devices. A
composite flag should be created for each of the end-point
status flags (EF and FF). The partial status flags (PAE and
PAF) can be detected from any one device. Figure 2 demon-
strates a 18-bit word width by using two CY7C4282V/92V. Any
word width can be attained by adding additional
CY7C4282V/92V.
When the CY7C4282V/92V is in a Width Expansion Configu-
ration, the Read Enable (REN) control input can be grounded
(see Figure 2). In this configuration, the Load (LD) pin is set to
LOW at Reset so that the pin operates as a control to load and
read the programmable flag offsets.
DATA IN (D) 18 9
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
PROGRAMMABLE(PAE)
HALF FULL FLAG (HF)
RESET (RS)
7C4282V
7C4292V
FULL FLAG (FF)
FF
EF
9
RESET (RS)
9
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
7C4282V
7C4292V
PROGRAMMABLE (PAF)
EMPTY FLAG (EF)
FF
EF
9 DATA OUT (Q) 18
FIRST LOAD (FL)
EXPANSION IN (XI)
FIRST LOAD (FL)
EXPANSION IN (XI)
Figure 2. Block Diagram of 64K × 9/128K × 9 Low-Voltage Deep Sync FIFO Memory
Used in a Width-Expansion Configuration
Notes:
2. n = Empty Offset (n = 7 default value).
3. m = Full Offset (m = 7 default value).
Document #: 38-06014 Rev. *B
Page 5 of 15
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