10XSD200 データシートの表示（PDF） - Freescale Semiconductor

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10XSD200

Dual 10 mOhm High Side Switch

Freescale Semiconductor 

mode, the FSOB pin returns to logic high and previously set

faults and SPI registers are reset, except bits POR,

PARALLEL and fault bits of latchable faults that had actually

been latched.

FAULT MODE

The device enters Fault mode when any of the following

faults occurs in Normal or Fail-safe mode:

• Overtemperature fault, (latchable fault)

• Overcurrent fault, (latchable fault)

• Severe short-circuit fault, (latchable fault)

• Output shorted to VPWR in OFF state (default: disabled)

• OpenLoad fault in OFF state (default: disabled)

• OpenLoad fault in ON state (default: disabled)

• External clock failure (default: enabled)

• Overvoltage fault (enabled by default)

• Undervoltage fault, (latchable fault)

The Fault Status pin (FSB) asserts a fault occurrence on

any channel in real time (active low). Additionally, the

assigned fault bit in the STATR_s or FAULTR_s register is

set to one. Conversely to the FSB pin, a fault bit remains set

until the corresponding register is read, even if the fault has

disappeared. These bits can be read via the SO pin. Fault

occurrence also results in a turn-off of the incurred channel,

except for the following faults: OpenLoad (On and Off state),

External Clock Failure and Output(s) shorted to VPWR. Under

and overvoltage occurrences cause simultaneous turn-off of

both channels. Details on the device’s behavior, after the

occurrence of one of the above faults can be found in

Protection and Diagnostic Features.

Fault mode (Operation and Operating Modes) is entered

when:

• VPWR (+VDD) were within the normal voltage range, and

• wake-up = 1, and

• fail-safe = X, and

• fault = 1 (see Going from Normal to Fail-safe, Fault or

Sleep Mode)

Resetting FAULT bits

Registers STATR_s and FAULTR_s contain global and

channel-specific fault information. Reading the register the

fault bit is contained in, clears it, provided a failure cause

disappearance has been detected and the fault wasn’t

latched.

Entering Fault Mode from Fail-safe Mode

When a Fault occurs in Fail-safe mode, the device is in

Fault/Fail-safe mode and behaves according to the

description of fault mode. However, SPI registers remain

reset and can not be accessed. Only the Direct inputs control

the channels.

Returning from Fault Mode to Fail-safe Mode

When disappearance of the fault previously produced in

Fail-safe mode has been detected, the device returns to Fail-

FUNCTIONAL DEVICE OPERATION

OPERATION AND OPERATING MODES

safe mode and behaves accordingly. FSB goes high, but the

auto-retry counter is not reset. Latched faults are not

delatched. SPI registers remain reset.

LATCHABLE FAULTS

An auto-retry function (see Auto-retry) controls how the

device responds to the so-called latchable faults. Latchable

faults are: overcurrent (OC), severe short-circuit (SC),

overtemperature (OT), and undervoltage (UV). If a latchable

fault occurs, the channel is turned off, the FSB pin goes low,

and the assigned fault bit is set. These bits can not be reset

before the next turn-on event is generated by auto-retry.

Next, the channel is automatically turned on at a

programmable interval, provided auto-retry was enabled and

the channel wasn’t latched.

If the failure disappears prior to the expiration of the

available number of auto-retries, the FSB pin automatically

returns to logic [1], but the fault bit remains set. It can still be

reset by reading out the SPI register in which it is contained.

However, the fault actually gets latched if the failure cause

hasn’t disappeared at the first turn-on event following

expiration of the available amount of auto-retries (see Auto-

retry). In that case, the channel gets latched and the FSB pin

remains low. The fault bit can only be reset by reading out the

associated SPI register, after having performed a delatch

sequence (Fault Delatching).

Fault Delatching

To delatch a latched channel and be able to turn it on

again, a delatch sequence must execute after the

disappearance of the failure cause. Delatching also allows to

reset the fault bit of latched faults (see Resetting FAULT bits).

To reset the FSB pin, both channels must be delatched.

Delatching is achieved by either alternating the state of the

channels’ fault control signal fc[x] (generating a 1_0_1

sequence), or by resetting the auto-retry counter (provided

retry is enabled). (See Reset of the Auto-retry Counter)

Delatching then actually occurs at the rising edge of the turn-

on event.

Signal fc[x] is an internal signal used by the device’s

internal logic circuitry to control the diagnostic functions. The

value of fc[x] depends on the state of the variables IN_ON[x],

DIR_dis[x] and ON[x] and is expressed as follows:

fc[x] = ((IN_ON[x] and DIR_dis[x] = 0) or ON[x] = 1)

Alternating the fc[x] signal is achieved differently according

to the way the user controls the device.

• In direct-input controlled mode (DIR_dis_s = 0), the IN[x]

pin must be set low, remain low for at least tIN seconds,

and set high again (be switched On). This might happen

automatically when operating at frequencies, f<4.0 Hz.

• In SPI-controlled mode, the ON_bit state (D8 of the

PWMR_s reg.) must be alternated (‘toggled’). No minimum

OFF state duration is required in this case.

Performing a delatch sequence anytime during an ongoing

auto-retry sequence (before latching) allows turning the

channel on unconditionally.

Analog Integrated Circuit Device Data

Freescale Semiconductor

10XSD200

29

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