10XSD200 データシートの表示（PDF） - Freescale Semiconductor
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10XSD200 Datasheet PDF : 60 Pages
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FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
FUNCTIONAL DEVICE OPERATION
OPERATION AND OPERATING MODES
The device possesses two high side switches (channels)
each of which can be controlled independently. The device
has four fundamental operating modes: Sleep, Normal, Fail-
safe, and Fault mode, as shown in Table 5.
Each channel can be controlled in three different ways in
Normal mode: by a signal on the Direct Input pin, by an
internal clock signal (autonomous operation) or by an
external clock signal. For bidirectional SPI communication, a
second supply voltage is required (VDD = 5,0 V or 3.3 V).
When only the direct inputs IN[x] are used, VDD isn’t required.
DEVICE START-UP SEQUENCE
To put the device in a known configuration and guarantee
predictable behavior, the device must undergo a wake-up
sequence. However, it should not be woken up earlier than
the moment at which VPWR has exceeded its undervoltage
threshold, VPWR(UV), and VDD has exceeded its supply
failure threshold, VDD(FAIL). In applications using the SPI
port, the device is typically put in wake mode by setting
RSTB=1. Wake-up of applications with direct input control
can be achieved by having signals IN_ON[0] = 1 or
IN_ON[1 ]= 1 (see Figure 10). After wake-up, all SPI register
contents are reset and Normal mode is entered (as defined in
Table 11 and Table 12). All the device functions are available
50 µs later (typically).
If the start-up sequence is not performed at device start-
up, its configuration may be undetermined and correct
operation is not guaranteed. In situations where the above
described start-up sequence can not be performed, it is
recommended to generate a wake-up event after the moment
VPWR has reached the undervoltage threshold.
CHANNEL CONFIGURATION THROUGH THE SPI
Setting the Channel Configuration
The channel configuration is determined by the contents of
the pulse-width (PWMR_s), the configuration (CONFR_s)
and the overcurrent (OCR_s) registers. They allow setting,
among others, the following parameters: duty-cycle, delay,
Slew Rate, PWM enable (PWM_en), clock selection
(CLOCK_sel), prescaler (PR), and direct_input disable
(DIR_dis). Extension “_s” means that these registers exist for
each of both channels. Function assignment is described in
detail in the section SI Register Addressing
Reading Back the Channel’s Status and Settings
The channel’s global switching and operating states (On/
Off, normal/fault) are all contained in the STATR register (see
Table 12). The precise fault type can be found by reading out
the FAULTR_s and STATR registers. The channel’ settings
(channel configuration) can be read back by reading the
PWMR, CONF, OCR, RETRY, GCR, and DIAG registers. For
more information, see Serial Output Register Assignment.
NORMAL MODE
Normal mode (bit NM = 1) can be entered in two ways,
either by driving the device through the direct inputs IN[x], or
by establishing SPI communication (requires RSTB =high).
Bidirectional SPI communication additionally requires the
presence of VDD. To maintain the device in Normal mode,
communication must take place regularly (see Entering and
Maintaining Normal Mode). The device is in Normal mode
(NM) when:
• VPWR (and VDD) are within the normal range and
• wake-up = 1, and
• fail-safe = 0, and
• fault = 0.
Channel Control in Normal Mode
In direct input mode, the channel’s switching state (On/Off)
basically follows the logic state of the direct input signal with
the turn-on delay and slew rate specified in Table 4.
In internal clock mode, the switching state is controlled by
an internal clock signal (Internal Clock & Internal PWM
(Clock_int_s bit = 1)). Frequency, slew rate, duty-cycle, and
turn-on delay are programmable independently for both
channels.
In external clock mode, the frequency of the external clock
controls the output's PWM frequency, but slew rate, duty
cycle, and turn-on delay are still programmable.
Factors Determining the Channel’s Switching State
The switching state of a channel is defined by the
instantaneous value of the output voltage. It is defined as
“On” when the output voltage V(HS[x]) > VPWR /2 and “Off”
when V(HS[x]) < VPWR /2. The channel’s switching state
should not be confused with the device’s internal channel
control state hson[x] (= High Side On). Signal hson[x] defines
the targeted switching state of the channel (On/Off). It is
either controlled by the value of the direct input signal or by
that of the internal/external clock signals combined with the
SPI register settings. The value of hson[x] is given by the
following boolean expression:
hson[x] = [(IN[x] and DIR_dis[x]) or (On bit [x] and
Duty_cycle[x] and PWM_en[x] = 1) or (On bit [x] and
PWM_en[x] = 0)].
In this expression Duty_cycle[x] represents the value of
the duty cycle, set by bits D7…D0 of the PWMR register
(Table 6). The channel’s actual switching state may differ
from the control signal’s state in the following cases:
• short circuits to GND, before automatic turn-Off (t < tFAULT)
• short circuits to VPWR when the channel is set to Off
10XSD200
Analog Integrated Circuit Device Data
26
Freescale Semiconductor
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