IMIC9835 データシートの表示（PDF） - Cypress Semiconductor
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IMIC9835
Cypress Semiconductor
IMIC9835 Datasheet PDF : 18 Pages
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C9835
Low-EMI Clock Generator for Intel®
Mobile 133-MHz/3 SO-DIMM Chipset Systems
Features
• Meets Intel’s Mobile 133.3MHz Chipset
• Three CPU Clocks (66.6/100/133.3 MHz, 2.5V)
• Six SDRAM Clocks, 1-DCLK (100/133.3 MHz, 3.3V)
• Seven PCI Clocks (33MHz, 3.3V), one free running
• Two IOAPIC clocks, synchronous to CPU clock (33.3
MHz, 2.5V)
• One REF Clock
• Two 48-MHz fixed non-SSCG clocks (USB and DOT)
• Three 3V66 clocks (66.6 MHz, 3.3V) ICH, HUBLINK, and
AGP memory
• One selectable frequency for VCH video channel clock
(48-MHz non-SSCG, 66.6-MHz CPU-SSCG, 3.3V)
• Power management using power-down, CPU stop, and
PCI stop pins
• Three function select pins (include test-mode select)
• Cypress Spread Spectrum for best electromagnetic
interference (EMI) reduction
• SMBUS support with readback
• 56-pin SSOP and TSSOP packages
Table 1. Function Table[1]
TEST#
0
0
1
1
1
1
SEL1
X
X
0
0
1
1
SEL0
0
1
0
1
0
1
CPU(0:2)
Hi-Z
TCLK/2
66.6
100.0
133.3
133.3
SDRAM(0:5)
DCLK
Hi-Z
TCLK/2
100.0[2]
100.0[2]
133.3
100.0[2]
3V66(0:2)
Hi-Z
TCLK/3
66.6
66.6
66.6
66.6
PCIF(1:6) 48M(0:1) REF IOAPIC(0:10)
Hi-Z
TCLK/6
33.3
33.3
33.3
33.3
Hi-Z
TCLK/2
48
48
48
48
Hi-Z
TCLK
14.318
14.318
14.318
14.318
Hi-Z
TCLK/6
33.3
33.3
33.3
33.3
Note:
1. These are the frequencies that are selectable after power up using the SEL1 and SEL0 hardware pins. Other frequencies may be chosen using the devices
SMBUS interface. See the expanded frequency for a complete listing of all of the availible frequencies.
2. Will be set to 133MHz, when SMBUS Byte3, Bit 0 is set to logic 1.
Block Diagram
Pin Configuration
X IN
XO U T
TEST#
S E L 0 ,1
P C I_ S T P #
C P U _S T P #
PD#
S C LK
SDATA
36pF
36pF
IO A P IC
CPU
R in
tris ta te
s0
PD#
SDRAM
3V66
i2 c -c lk
i2 c -d a ta
PLL1
R in
48
PD#
i2 c -c lk
i2 c -d a ta
PLL2
PCI
VDD
1
VDD
1
VDDI
REF
VC H _C LK
2
IO A P IC (0 ,1 )
VDDC
3
C P U (0:2 )
VDDS
6
VDD
3
VDDP
S D R A M (0 :5 )
3 V 6 6 (0 :2 )
P C I_ F
VDDP
6
P C I(1 :6 )
VDD
2
4 8 M (0 ,1 )
VDDS
1
D C LK
REF 1
VDD 2
XIN 3
XOUT 4
VSS 5
VSS 6
3V66_0 7
3V66_1 8
3V66_2(AGP) 9
VDD 10
PCI_STP# 11
PCI_F 12
PCI1 13
VSS 14
PCI2 15
PCI3 16
VDDP 17
PCI4 18
PCI5 19
PCI6 20
VSS 21
AVDD 22
AVSS 23
VSS 24
48M0(USB) 25
48M1(DOT) 26
VDD 27
SEL0 28
56
VSS
55
IO A P IC 0
54
IO A P IC 1
53
VDDI
52
CPU0
51
VDDC
50
CPU1
49
CPU2
48
VSS
47
VSS
C
46
45
SDRAM0
SDRAM1
9
44
VDDS
8
43
SDRAM2
3
42
41
SDRAM3
VSS
5
40
SDRAM4
39
SDRAM5
38
DCLK
37
VDDS
36
VCH_CLK
35
VDD
34
CPU_STP#
33
TEST#
32
PD#
31
SCLK
30
SDATA
29
SEL1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07303 Rev. **
Revised April 5, 2002
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