XRT84L38 データシートの表示（PDF） - Exar Corporation

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XRT84L38

OCTAL T1/E1/J1 FRAMER

Exar Corporation 

XRT84L38

OCTAL T1/E1/J1 FRAMER

REV. 1.0.1

13.2.4.1 HOW TO CONFIGURE THE RECEIVE HDLC CONTROLLER BLOCK TO RECEIVE MOS MESSAGE............................. 415

DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H) ...................... 415

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X00H) .............................. 416

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ......................................... 416

DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H) ...................... 416

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ......................................... 417

DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H) ...................... 417

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ......................................... 417

RECEIVE DATA LINK BYTE COUNT REGISTER (RDLBCR) (INDIRECT ADDRESS = 0XN0H, 0X15H) .............. 418

RECEIVE DATA LINK BYTE COUNT REGISTER (RDLBCR) (INDIRECT ADDRESS = 0XN0H, 0X15H) .............. 418

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ......................................... 418

13.2.5 RECEIVE SLCÂ96 DATA LINK CONTROLLER ...................................................................................................... 419

RECEIVE SLC®96 MESSAGE REGISTERS .................................................................................................. 419

13.2.5.1 HOW TO CONFIGURE THE SLC®96 DATA LINK CONTROLLER TO RECEIVE SLC®96 DATA LINK MESSAGES ....... 419

DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H) ...................... 420

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X00H) .............................. 420

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) .......................................... 420

DATA LINK INTERRUPT ENABLE REGISTER (DLIER) (INDIRECT ADDRESS = 0XNAH, 0X07H) ...................... 421

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ......................................... 421

RECEIVE DATA LINK BYTE COUNT REGISTER (RDLBCR) (INDIRECT ADDRESS = 0XN0H, 0X15H) .............. 421

14.0 E1 HDLC CONTROLLER BLOCK ..................................................................................................... 423

14.1 E1 TRANSMIT HDLC CONTROLLER BLOCK ............................................................................................. 423

14.1.1 DESCRIPTION OF THE E1 TRANSMIT HDLC CONTROLLER BLOCK ................................................................ 423

SYNCHRONIZATION MUX REGISTER (SMR) (INDIRECT ADDRESS = 0XN0H, 0X09H) .................................. 423

DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H) ...................................... 424

14.1.2 HOW TO CONFIGURE XRT84L38 TO TRANSMIT DATA LINK INFORMATION THROUGH THE NATIONAL BITS (SA4

THROUGH SA8)........................................................................................................................................................... 424

TRANSMIT SIGNALING AND DATA LINK SELECT REGISTER (TSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH) 424

TRANSMIT SIGNALING AND DATA LINK SELECT REGISTER (TSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH) 425

14.1.3 HOW TO CONFIGURE XRT84L38 TO TRANSMIT DATA LINK INFORMATION THROUGH TIMESLOT 16 OCTET 425

TRANSMIT SIGNALING AND DATA LINK SELECT REGISTER (TSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH) 425

14.1.4 HOW TO CONFIGURE XRT84L38 TO TRANSMIT DATA LINK INFORMATION THROUGH D OR E CHANNELS 425

TRANSMIT CHANNEL CONTROL REGISTER (TCCR) (INDIRECT ADDRESS = 0XN2H, 0X00H - 0X1FH) .......... 426

14.1.5 TRANSMIT BOS (BIT ORIENTED SIGNALING) PROCESSOR .............................................................................. 426

14.1.6 TRANSMIT MOS (MESSAGE ORIENTED SIGNALING) OR LAPD CONTROLLER .............................................. 426

14.2 E1 RECEIVE HDLC CONTROLLER BLOCK................................................................................................ 426

14.2.1 DESCRIPTION OF THE E1 RECEIVE HDLC CONTROLLER BLOCK ................................................................... 426

DATA LINK STATUS REGISTER (DLSR) (INDIRECT ADDRESS = 0XNAH, 0X06H) ......................................... 427

14.2.2 HOW TO CONFIGURE XRT84L38 TO RECEIVE DATA LINK INFORMATION THROUGH THE NATIONAL BITS (SA4

THROUGH SA8)........................................................................................................................................................... 427

RECEIVE SIGNALING AND DATA LINK SELECT REGISTER (RSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0CH) 428

RECEIVE SIGNALING AND DATA LINK SELECT REGISTER (RSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0CH) 428

14.2.3 HOW TO CONFIGURE XRT84L38 TO RECEIVE DATA LINK INFORMATION THROUGH TIMESLOT 16 OCTET 428

RECEIVE SIGNALING AND DATA LINK SELECT REGISTER (RSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0CH) 429

14.2.4 HOW TO CONFIGURE XRT84L38 TO RECEIVE DATA LINK INFORMATION THROUGH D OR E CHANNELS 429

RECEIVE CHANNEL CONTROL REGISTER (RCCR) (INDIRECT ADDRESS = 0XN2H, 0X60H - 0X7FH) ........... 429

14.2.5 RECEIVE BOS (BIT ORIENTED SIGNALING) PROCESSOR................................................................................. 429

14.2.6 RECEIVE LAPD CONTROLLER .............................................................................................................................. 429

15.0 TRANSMIT LIU INTERFACE ............................................................................................................. 431

16.0 RECEIVE LIU INTERFACE ................................................................................................................ 431

ORDERING INFORMATION ................................................................................................................ 432

PACKAGE DIMENSIONS .............................................................................................................................. 432

REVISIONS ................................................................................................................................................ 433

XIV

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