XRT84L38 データシートの表示（PDF） - Exar Corporation

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XRT84L38

OCTAL T1/E1/J1 FRAMER

Exar Corporation 

XRT84L38

OCTAL T1/E1/J1 FRAMER

REV. 1.0.1

THIRD OCTET OF 16.384MBIT/S DATA STREAM.......................................................................................... 296

FIFTH OCTET OF 16.384MBIT/S DATA STREAM .......................................................................................... 296

SEVENTH OCTET OF 16.384MBIT/S DATA STREAM..................................................................................... 296

SECOND OCTET OF 16.384MBIT/S DATA STREAM ...................................................................................... 297

FOURTH OCTET OF 16.384MBIT/S DATA STREAM ...................................................................................... 297

SIXTH OCTET OF 16.384MBIT/S DATA STREAM .......................................................................................... 297

EIGHTH OCTET OF 16.384MBIT/S DATA STREAM ....................................................................................... 297

FIGURE 95. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT USING 16.384MBIT/S DATA BUS ......................................... 298

FIGURE 96. TIMING SIGNAL WHEN THE FRAMER IS RUNNING AT HMVIP 16.384MBIT/S MODE ......................................................... 298

6.2.3.6 E1 RECEIVE INPUT INTERFACE - H.100 16.384MBIT/S......................................................................................... 298

FIRST OCTET OF 16.384MBIT/S DATA STREAM .......................................................................................... 299

THIRD OCTET OF 16.384MBIT/S DATA STREAM.......................................................................................... 299

FIFTH OCTET OF 16.384MBIT/S DATA STREAM .......................................................................................... 299

SEVENTH OCTET OF 16.384MBIT/S DATA STREAM..................................................................................... 299

SECOND OCTET OF 16.384MBIT/S DATA STREAM ...................................................................................... 300

FOURTH OCTET OF 16.384MBIT/S DATA STREAM ...................................................................................... 300

SIXTH OCTET OF 16.384MBIT/S DATA STREAM .......................................................................................... 300

EIGHTH OCTET OF 16.384MBIT/S DATA STREAM ....................................................................................... 300

FIGURE 97. INTERFACING XRT84L38 TO LOCAL TERMINAL EQUIPMENT USING 16.384MBIT/S DATA BUS ......................................... 301

FIGURE 98. TIMING SIGNAL WHEN THE FRAMER IS RUNNING AT H.100 16.384MBIT/S MODE ........................................................... 301

7.0 DS1 OVERHEAD INTERFACE BLOCK .............................................................................................. 302

7.1 DS1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK........................................................................... 302

7.1.1 DESCRIPTION OF THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK .............................................. 302

FIGURE 99. BLOCK DIAGRAM OF THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE OF THE XRT84L38 ........................................ 302

7.1.2 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE FACILITY DATA

LINK (FDL) BITS IN ESF FRAMING FORMAT MODE ............................................................................................... 302

TRANSMIT DATA LINK SELECT REGISTER (TDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH)........................ 303

TRANSMIT DATA LINK SELECT REGISTER (TDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH)........................ 303

FIGURE 100. DS1 TRANSMIT OVERHEAD INPUT INTERFACE TIMING IN ESF FRAMING FORMAT MODE ............................................. 303

7.1.3 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE SIGNALING

FRAMING (FS) BITS IN N OR SLC®96 FRAMING FORMAT MODE......................................................................... 304

TRANSMIT DATA LINK SELECT REGISTER (TDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH)........................ 304

FIGURE 101. DS1 TRANSMIT OVERHEAD INPUT TIMING IN N OR SLC®96 FRAMING FORMAT MODE .............................................. 304

7.1.4 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE REMOTE SIG-

NALING (R) BITS IN T1DM FRAMING FORMAT MODE............................................................................................ 304

TRANSMIT DATA LINK SELECT REGISTER (TDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH) ........................... 305

FIGURE 102. DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE IN T1DM FRAMING FORMAT MODE ........................................ 305

7.2 DS1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ......................................................................... 306

7.2.1 DESCRIPTION OF THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ............................................. 306

FIGURE 103. BLOCK DIAGRAM OF THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE OF XRT84L38............................................ 306

7.2.2 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE FACILITY

DATA LINK (FDL) BITS IN ESF FRAMING FORMAT MODE .................................................................................... 306

RECEIVE DATA LINK SELECT REGISTER (TDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH).......................... 307

RECEIVE DATA LINK SELECT REGISTER (TDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH).......................... 307

FIGURE 104. DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE IN ESF FRAMING FORMAT MODE........................................... 308

7.2.3 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE SIGNALING

FRAMING (FS) BITS IN N OR SLC®96 FRAMING FORMAT MODE......................................................................... 308

RECEIVE DATA LINK SELECT REGISTER (TDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH)......................... 308

FIGURE 105. DS1 RECEIVE OVERHEAD OUTPUT INTERFACE TIMING IN N OR SLC®96 FRAMING FORMAT MODE ............................ 309

7.2.4 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE REMOTE

SIGNALING (R) BITS IN T1DM FRAMING FORMAT MODE ..................................................................................... 309

RECEIVE DATA LINK SELECT REGISTER (RDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH) ........................ 309

FIGURE 106. DS1 RECEIVE OVERHEAD OUTPUT INTERFACE TIMING IN T1DM FRAMING FORMAT MODE......................................... 310

8.0 E1 OVERHEAD INTERFACE BLOCK ................................................................................................. 311

8.1 E1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK ............................................................................. 311

8.1.1 DESCRIPTION OF THE E1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK................................................. 311

FIGURE 107. BLOCK DIAGRAM OF THE E1 TRANSMIT OVERHEAD INPUT INTERFACE OF XRT84L38 ................................................ 311

8.1.2 CONFIGURE THE E1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE NATIONAL BIT SE-

QUENCE IN E1 FRAMING FORMAT MODE............................................................................................................... 311

SYNCHRONIZATION MUX REGISTER (SMR) (INDIRECT ADDRESS = 0XN0H, 0X09H) .................................. 312

TRANSMIT SIGNALING AND DATA LINK SELECT REGISTER (TSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH) 312

VIII

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