XRT84L38 データシートの表示（PDF） - Exar Corporation

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XRT84L38

OCTAL T1/E1/J1 FRAMER

Exar Corporation 

XRT84L38

OCTAL T1/E1/J1 FRAMER

REV. 1.0.1

RECEIVE USER IDLE CODE REGISTER (UCR) (INDIRECT ADDRESS = 0XN02H, 0X80H - 0X97H) ............... 376

12.4 HOW TO CONFIGURE THE XRT84L38 FRAMER TO EXTRACT ROBBED-BIT SIGNALING INFORMATION

376

12.4.1 CONFIGURE THE FRAMER TO RECEIVE AND EXTRACT ROBBED-BIT SIGNALING....................................... 376

RECEIVE SIGNALING CONTROL REGISTER (RSCR) (INDIRECT ADDRESS = 0XN2H, 0XA0H - 0XB7H) ......... 376

FRAMER INTERRUPT ENABLE REGISTER (FIER) (INDIRECT ADDRESS = 0XNAH, 0X05H) ............................. 377

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X00H) .............................. 377

FRAMER INTERRUPT STATUS REGISTER (FISR) (INDIRECT ADDRESS = 0XNAH, 0X04H) ............................ 377

SIGNALING CHANGE REGISTERS (SCR) (INDIRECT ADDRESS = 0XN0H, 0X0DH - 0X10H) .......................... 378

12.4.1.1 STORE SIGNALING BITS INTO RSRA REGISTER ARRAY ..................................................................................... 378

RECEIVE SIGNALING REGISTER ARRAY (RSRA) (INDIRECT ADDRESS = 0XN4H, 0X00H - 0X1FH) .............. 378

12.4.1.2 OUTPUTTING SIGNALING BITS THROUGH RXSIG_N PIN ...................................................................................... 378

RECEIVE INTERFACE CONTROL REGISTER (RICR) (INDIRECT ADDRESS = 0XN0H, 0X20H)......................... 379

FIGURE 125. TIMING DIAGRAM OF RXSIG_N OUTPUT PIN .............................................................................................................. 379

12.4.1.3 OUTPUTTING SIGNALING BITS FROM RXOH_N PIN ............................................................................................ 379

FIGURE 126. TIMING DIAGRAM OF THE RXOH_N OUTPUT PIN........................................................................................................ 379

RECEIVE SIGNALING CONTROL REGISTER (RSCR) (INDIRECT ADDRESS = 0XN2H, 0XA0H - 0XBFH) .......... 380

12.4.1.4 SEND SIGNALING DATA THROUGH RXSER_N PIN............................................................................................... 380

12.4.1.5 SIGNALING DATA SUBSTITUTION ....................................................................................................................... 380

RECEIVE SIGNALING CONTROL REGISTER (RSCR) (INDIRECT ADDRESS = 0XN2H, 0XA0H - 0XBFH) ......... 380

RECEIVE SUBSTITUTION SIGNALING REGISTER (RSSR) (INDIRECT ADDRESS = 0XN02H, 0X80H - 0X9FH) . 380

RECEIVE SIGNALING CONTROL REGISTER (RSCR) (INDIRECT ADDRESS = 0XN2H, 0X40H - 0X5FH).......... 381

12.5 HOW TO CONFIGURE THE FRAMER TO DETECT ALARMS AND ERROR CONDITIONS...................... 381

12.5.1 HOW TO CONFIGURE THE FRAMER TO DETECT AIS ALARM........................................................................... 381

ALARM GENERATION REGISTER (AGR) (INDIRECT ADDRESS = 0XN0H, 0X08H) ......................................... 383

ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH, 0X03H)......... 383

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H) .............................. 383

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ............................ 384

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ............................ 384

12.5.2 HOW TO CONFIGURE THE FRAMER TO DETECT RED ALARM ......................................................................... 384

ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH, 0X03H)......... 385

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H) .............................. 385

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ........................... 385

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ........................... 386

12.5.3 HOW TO CONFIGURE THE FRAMER TO DETECT YELLOW ALARM ................................................................. 386

ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH, 0X03H).......... 386

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H) .............................. 386

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ........................... 387

12.5.4 HOW TO CONFIGURE THE FRAMER TO DETECT CAS MULTI-FRAME YELLOW ALARM............................... 387

ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH, 0X03H)......... 387

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H) .............................. 388

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ........................... 388

12.5.5 HOW TO CONFIGURE THE FRAMER TO DETECT BIPOLAR VIOLATION .......................................................... 388

ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH, 0X03H)......... 389

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H) ............................... 389

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ............................ 389

12.5.6 HOW TO CONFIGURE THE FRAMER TO DETECT LOSS OF SIGNAL ................................................................ 389

ALARM AND ERROR INTERRUPT ENABLE REGISTER (AEIER) (INDIRECT ADDRESS = 0XNAH, 0X03H).......... 390

BLOCK INTERRUPT ENABLE REGISTER (BIER) (INDIRECT ADDRESS = 0XNAH, 0X01H) ............................... 390

ALARM AND ERROR STATUS REGISTER (AESR) (INDIRECT ADDRESS = 0XNAH, 0X02H) ............................ 390

13.0 DS1 HDLC CONTROLLER BLOCK .................................................................................................. 390

13.1 DS1 TRANSMIT HDLC CONTROLLER BLOCK .......................................................................................... 390

13.1.1 DESCRIPTION OF THE DS1 TRANSMIT HDLC CONTROLLER BLOCK .............................................................. 390

TRANSMIT DATA LINK SELECT REGISTER (TSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0AH) .................... 391

DATA LINK CONTROL REGISTER (DLCR) INDIRECT ADDRESS = 0XN0H, 0X13H)......................................... 392

DATA LINK CONTROL REGISTER (DLCR) (INDIRECT ADDRESS = 0XN0H, 0X13H) ....................................... 392

13.1.2 HOW TO CONFIGURE XRT84L38 TO TRANSMIT DATA LINK INFORMATION THROUGH D OR E CHANNELS 392

TRANSMIT CHANNEL CONTROL REGISTER (TCCR) (INDIRECT ADDRESS = 0XN2H, 0X00H - 0X1FH) ........... 392

XII

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