V370PDC データシートの表示（PDF） - QuickLogic Corporation

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V370PDC

High Performance PCI SDRAM Controller with Integrated Peripheral Control Unit

QuickLogic Corporation 

V370PDC

3.6 Serial EEPROM Port TImings

The clock for the serial EEPROM interface is derived by dividing the PCI bus clock. The waveforms

generated are shown in Figure 4.

Figure 4: Serial EEPROM Waveforms and Timing

START CONDITION

512 PCI BUS

CLOCKS

STOP CONDITION

SCL

SDA

256 PCI BUS

CLOCKS

256 PCI BUS

CLOCKS

4.0 Revision History

Table 14: Revision Histo r

Revision Date

Number

Comments and Changes

0.8

01/99 First pre-silicon revision of preliminary data sheet.

Update Figure 2: Mechanical Drawing;

0.9

03/99

Update Table 8: Local Bus Signals DC Operating Specifications;

Update Table 10: Local Bus ACTest Conditions;

Update Table 12: Local Bus Signals AC Operating Specifications.

1.0

03/99 Initial Release.

USA:

2348G Walsh Avenue

Santa Clara, CA 95051

Phone: (408)988-1050 Fax: (408)988-2601

Toll Free: (800)488-8410 (Canada and U.S. only)

World Wide Web: http://www.vcubed.com

14

V370PDC_A0 Data Sheet Rev 1.00 DS-PD01-0100

Copyright © 1999, V3 Semiconductor Inc.

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