V370PDC データシートの表示（PDF） - QuickLogic Corporation
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V370PDC
QuickLogic Corporation
V370PDC Datasheet PDF : 14 Pages
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V370PDC
Table 12: Local Bus iming Parameters for Vcc =3.3 Volts +/- 5%
66MHz
# Symbol
Description
Notes Min Max Units
1 TC CLKIN period
2 TCH CLKIN high time
3 TCL CLKIN low time
4 TSU Synchronous input setup
4a TSU Synchronous input setup (READY)
5 TH Synchronous input hold
6 TCOV CLKIN to output valid delay
7 TCZO CLKIN to output driving delay
8 TCOZ CLKIN to high impedance delay
9 TALE ALE Pulse Width
10 TCLH CLKIN rising to ALE rising
11 TAH CLKIN falling to ALE falling
15
ns
5.5
ns
5.5
ns
3
ns
1
TBA
ns
1
ns
3
11
ns
3
11
ns
4
12
ns
TCH+0.5 TCH+1 ns
2
10
ns
2
10
ns
Notes:
1. Applies only to READY pin when i960_RDY bit in LB_BUS_CFG register is set to ’1’.
Table 13: PCI Bus Timing Parameters for Vcc = 3.3 Volts +/- 10%
# Symbol
Description
1
TC PCLK period
2
TSU Synchronous input setup to PCLK
3
TH Synchronous input hold from PCLK
4 TCOV PCLK to output valid delay
5 TCZO PCLK to output driving delay
6 TCOZ PCLK to high impedance delay
7 TRST Reset period when PRST used as input
Notes Min Max Units
30
ns
1
7
ns
0
ns
2
3
11 ns
4
11 ns
5
18 ns
16·TC
Copyright © 1999, V3 Semiconductor Corp.
V370PDC_A0 Data Sheet Rev 1.00 DS-PD01-0100
13
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