PEF2256 データシートの表示（PDF） - Infineon Technologies

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PEF2256

Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

Infineon Technologies 

FALC®56

PEF 2256 H/E

Introduction

1

Introduction

The FALC®56 framer and line interface component is designed to fulfill all required

interfacing between analog E1/T1/J1 lines and the digital PCM system highway,

H.100/H.110 or H-MVIP bus for world market telecommunication systems.

Due to its multitude of implemented functions, it fits to a wide range of networking

applications and fulfills the according international standards. Three integrated signaling

controllers including Signaling System #7 (SS7) support reduces software overhead.

Crystal-less jitter attenuation with only one master clock source, integrated receive line

termination, and an analog switch reduce the amount of required external components.

Equipped with a flexible microprocessor interface, it connects to any control processor

environment. A standard boundary scan interface is provided to support board level

testing. Flat pack or BGA device packaging, minimum number of external components

and low power consumption lead to reduced overall system costs.

User’s Manual

17

Hardware Description

DS1.1, 2003-10-23

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