PEF2256 データシートの表示（PDF） - Infineon Technologies
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PEF2256
Infineon Technologies
PEF2256 Datasheet PDF : 518 Pages
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FALC®56
PEF 2256 H/E
List of Figures
Page
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Single Channel Loop-Back (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Receive Clock System (T1/J1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Receiver Configuration (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Receive Line Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Protection Switching Application (T1/J1) . . . . . . . . . . . . . . . . . . . . . . 127
Long Haul Protection Switching Application (T1/J1) . . . . . . . . . . . . . 128
Jitter Attenuation Performance (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . 131
Jitter Tolerance (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
The Receive Elastic Buffer as Circularly Organized Memory . . . . . . 137
Automatic Handling of Errored Signaling Units . . . . . . . . . . . . . . . . . 140
Influences on Synchronization Status (T1/J1) . . . . . . . . . . . . . . . . . . 145
Transmitter Configuration (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Clocking in Remote Loop Configuration (T1/J1) . . . . . . . . . . . . . . . . 162
Transmit Clock System (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Transmit Line Monitor Configuration (T1/J1) . . . . . . . . . . . . . . . . . . . 167
System Interface (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Receive System Interface Clocking (T1/J1) . . . . . . . . . . . . . . . . . . . . 174
SYPR Offset Programming (1.544 Mbit/s, 1.544 MHz) . . . . . . . . . . . 176
SYPR Offset Programming (6.176 Mbit/s, 6.176 MHz) . . . . . . . . . . . 176
RFM Offset Programming (1.544 Mbit/s, 1.544 MHz) . . . . . . . . . . . . 177
RFM Offset Programming (6.176 Mbit/s, 6.176 MHz) . . . . . . . . . . . . 177
2.048 MHz Receive Signaling Highway (T1/J1). . . . . . . . . . . . . . . . . 178
Receive FS/DL-Bits in Time Slot 0 on RDO (T1/J1) . . . . . . . . . . . . . 178
1.544 MHz Receive Signaling Highway (T1/J1). . . . . . . . . . . . . . . . . 179
Transmit System Clocking: 1.544 MHz (T1/J1) . . . . . . . . . . . . . . . . . 180
Transmit System Clocking: 8.192 MHz/4.096 Mbit/s (T1/J1) . . . . . . . 181
2.048 MHz Transmit Signaling Clocking (T1/J1) . . . . . . . . . . . . . . . . 182
1.544 MHz Transmit Signaling Highway (T1/J1) . . . . . . . . . . . . . . . . 182
Signaling Marker for CAS/CAS-CC Applications (T1/J1) . . . . . . . . . . 183
Signaling Marker for CAS-BR Applications (T1/J1) . . . . . . . . . . . . . . 184
Transmit FS/DL Bits on XDI (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . 185
SYPX Offset Programming (1.544 Mbit/s, 1.544 MHz) . . . . . . . . . . . 186
SYPX Offset Programming (6.176 Mbit/s, 6.176 MHz) . . . . . . . . . . . 186
Remote Loop (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
Payload Loop (T1/J1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Local Loop (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Channel Loop-Back (T1/J1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
HDLC Receive Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
HDLC Transmit Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Interrupt Driven Data Transmission (flow diagram) . . . . . . . . . . . . . . 217
Interrupt Driven Transmission Example . . . . . . . . . . . . . . . . . . . . . . . 217
Interrupt Driven Reception Sequence Example . . . . . . . . . . . . . . . . . 218
User’s Manual
11
Hardware Description
DS1.1, 2003-10-23
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