PEF2256 データシートの表示（PDF） - Infineon Technologies

部品番号

コンポーネント説明

メーカー

PEF2256

Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

Infineon Technologies 

FALC®56

PEF 2256 H/E

Introduction

• Programmable elastic buffer size: 2 frames/1 frame/short buffer/bypass

• Provides different time slot mapping modes

• Supports fractional E1 or T1/J1 access

• Flexible transparent modes

• Programmable in-band loop code detection and generation (TR62411)

• Channel loop back, line loop back or payload loop back capabilities (TR54016)

• Pseudo-random binary sequence generator and monitor

(framed or unframed)

• Clear channel capabilities (T1/J1)

• Loop-timed mode

Signaling Controller

• Three HDLC controllers

Bit stuffing, CRC check and generation, flag generation, flag and address

recognition, handling of bit oriented functions

• Each HDLC controller selectable to operate on either line or system side

• Supports signaling system #7

delimitation, alignment and error detection according to ITU-Q.703

processing of fill in signaling units, processing of errored signaling units

• CAS/CAS-BR controller with last look capability, enhanced CAS-register access and

freeze signaling indication

• DL-channel protocol for ESF format according to ANSI T1.403 specification or

according to AT&T TR54016 (T1/J1)

• DL-bit access for F72 (SLC96) format (T1/J1)

• Generates periodical performance report according to ANSI T1. 403

• Provides access to serial signaling data streams

• Multiframe synchronization and synthesis according to ITU-T G.732

• Alarm insertion and detection (AIS and LOS in time slot 16)

• Transparent mode

• FIFO buffers (64 bytes deep) for efficient transfer of data packets

• Time slot assignment

Any combination of time slots selectable for data transfer independent of signaling

mode (useful for fractional T1/J1 applications)

• Time-slot 0 Sa8...4-bit handling via FIFOs (E1)

• HDLC access to any Sa-bit combination (E1)

Microprocessor Interface

• 8/16-bit microprocessor bus interface (Intel or Motorola type)

• All registers directly accessible (byte or word access)

• Multiplexed and non-multiplexed address bus operations

• Hard/software reset options

• Extended interrupt capabilities

User’s Manual

20

Hardware Description

DS1.1, 2003-10-23

Share Link: