PEF2256 データシートの表示（PDF） - Infineon Technologies

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コンポーネント説明

一致するリスト

PEF2256

Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications

Infineon Technologies 

FALC®56

PEF 2256 H/E

List of Figures

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GSM Base Station Aplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Pin Configuration P-MQFP-80-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Pin Configuration P-LBGA-81-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

FIFO Word Access (Intel Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

FIFO Word Access (Motorola Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Block Diagram of Test Access Port and Boundary Scan . . . . . . . . . . . 56

JTAG TAP Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Flexible Master Clock Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Single Voltage Power Supply Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Dual Voltage Power Supply Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Decoupling Capacitor Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Receive Clock System (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Receiver Configuration (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Receive Line Monitoring (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Short Haul Protection Switching Application (E1) . . . . . . . . . . . . . . . . 68

Long Haul Protection Switching Application (E1). . . . . . . . . . . . . . . . . 69

Jitter Attenuation Performance (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Jitter Tolerance (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

The Receive Elastic Buffer as Circularly Organized Memory . . . . . . . 76

Automatic Handling of Errored Signaling Units . . . . . . . . . . . . . . . . . . 79

2.048 MHz Receive Signaling Highway (E1) . . . . . . . . . . . . . . . . . . . . 81

CRC4 Multiframe Alignment Recovery Algorithms (E1). . . . . . . . . . . . 92

Transmitter Configuration (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Transmit Clock System (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Transmit Line Monitor Configuration (E1) . . . . . . . . . . . . . . . . . . . . . 102

2.048 MHz Transmit Signaling Highway (E1) . . . . . . . . . . . . . . . . . . 104

System Interface (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Receive System Interface Clocking (E1) . . . . . . . . . . . . . . . . . . . . . . 108

SYPR Offset Programming (2.048 Mbit/s, 2.048 MHz) . . . . . . . . . . . 110

SYPR Offset Programming (8.192 Mbit/s, 8.192 MHz) . . . . . . . . . . . 110

RFM Offset Programming (2.048 Mbit/s, 2.048 MHz) . . . . . . . . . . . . 111

RFM Offset Programming (8.192 Mbit/s, 8.192 MHz) . . . . . . . . . . . . 111

Transmit System Interface Clocking: 2.048 MHz (E1) . . . . . . . . . . . . 112

Transmit System Interface Clocking: 8.192 MHz/4.096 Mbit/s (E1). . 113

SYPX Offset Programming (2.048 Mbit/s, 2.048 MHz) . . . . . . . . . . . 115

SYPX Offset Programming (8.192 Mbit/s, 8.192 MHz) . . . . . . . . . . . 115

Remote Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Payload Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Local Loop (E1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

User’s Manual

10

Hardware Description

DS1.1, 2003-10-23

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