PDI1394L21 データシートの表示（PDF） - Philips Electronics

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PDI1394L21

1394 full duplex AV link layer controller

Philips Electronics 

Philips Semiconductors

1394 full duplex AV link layer controller

Preliminary specification

PDI1394L21

13.1 Link Control Registers

13.1.1 ID Register (IDREG) – Base Address: 0x000

The ID register is automatically updated by the attached PHY with the proper Node ID after completion of the bus reset.

3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BUS ID

NODE ID

PART CODE

VERSION CODE

SV00915

Reset Value 0xFFFF0101

Bit 31..22:

R/W BUS ID: The 10-bit bus number that is used with the Node ID in the source address for outgoing packets and used to

accept or reject incoming packets. This field reverts to all ‘1’s (0x3FF) upon bus reset.

Bit 21..16:

R/W NODE ID: Used in conjunction with Bus ID in the source address for outgoing packets and used to accept or reject

incoming packets. This register auto-updates with the node ID assigned after the 1394 bus Tree-ID sequence.

Bit 15..8:

R

PART CODE: “01” designates PDI1394L21.

Bit 7..0:

R

VERSION CODE: “02” shows this is revision level 2 of this part.

13.1.2 General Link Control (LNKCTL) – Base Address: 0x004

The General Link control register is used to program the Link Layer isochronous transceiver, as well as the overall link transceiver. It also

provides general link status.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BSYCTRL

ATACK

SV00892

Reset Value 0x46000002

Bit 31:

R/W IDValid (IDVALID): When equal to one, the PDI1394L21 accepts the packets addressed to this node. This bit is

automatically set after selfID complete and node ID is updated.

Bit 30:

R/W Receive Self ID (RCVSELFID): When asserted, the self-identification packets, generated by each PHY device on the

bus, during bus initialization are received and placed into the asynchronous request queue as a single packet. Bit 30

also enables the reception of PHY configuration packets in the asynchronous request queue.

Bit 29..27:

R/W Busy Control (BSYCTRL): These bits control what busy status the chip returns to incoming packets. The field is

defined below:

000 = use protocol requested by received packet (either dual phase or single phase)

001 = send busy A when it is necessary to send a busy acknowledge (testing/diagnostics)

010 = send a busy B when it is necessary to send a busy acknowledge (testing/diagnostics)

011 = use single phase retry protocol

100 = use protocol requested in packet, always send a busy ack (for all packets)

101 = busy A all incoming packets

110 = busy B all incoming packets are ‘1’

111 = use single phase retry protocol, always send a busy ack

Bit 26:

R/W Transmitter Enable (TxENABLE): When this bit is set, the link layer transmitter will arbitrate and send packets.

Bit 25:

R/W Receiver Enable (RxENABLE): When this bit is set, the link layer receiver will receive and respond to bus packets.

Bit 21:

R/W Reset Transmitter (RSTTx): When set to one, this synchronously resets the transmitter within the link layer.

Bit 20:

R/W Reset Receiver (RSTRx): When set to one, this synchronously resets the receiver within the link layer.

Bit 12:

R/W Strict Isochronous (STRICTISOCH): Used to accept or reject isochronous packets sent outside of specified

isochronous cycles (between a Cycle Start and subaction gap). A ‘1’ rejects packets sent outside the specified

cycles, a “0” accepts isochronous packets sent outside the specified cycle.

Bit 11:

R/W Cycle Master (CYMASTER): When asserted and the PDI1394L21 is attached to the root PHY (ROOT bit = 1), and

the cycle_count field of the cycle timer register increments, the transmitter sends a cycle-start packet. Cycle Master

function will be disabled if a cycle timeout is detected (CYTMOUT bit 5 in LNKPHYINTACK). To restart the Cycle

Master function in such a case, first reset CYMASTER, then set it again.

1999 Aug 06

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