NJU3502L データシートの表示（PDF） - Japan Radio Corporation

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NJU3502L

4-BIT SINGLE CHIP MICRO CONTROLLER

Japan Radio Corporation  

NJU3502

s INTERRUPT

The NJU3502 prepares three kinds of the interrupt. The interrupt "enable" or "disable" is controlled by the

program. The interrupt operates as single process and no multiple. However, when new interrupt request

occurs during the other interrupt process, the request is kept, and then the new interrupt process starts after

the prior interrupt process. The priority order of the interrupt is that the first is (1)External interrupt-1, the

second is (2)Internal interrupt-1, and the third is (3)Internal interrupt-2, as shown below.

When the interrupt request flag is set by the own factor, the interrupt enabled by the interrupt control

register(PHY5) stores the data of Program Counter, Accumulator, X-reg, X'-reg, Y-reg, Y'-reg, RPC, and

STATUS into the STACK register, and sets the interrupt vector address into Program Counter, and then the

interrupt process is started. The return from the interrupt process by "RETI" instruction resets the

corresponded interrupt request flag, and regains the held data from STACK, and then the operation before the

interrupt process is started continuously. When the interrupt control register disables the interrupt process, the

interrupt request flag is not set.

[THE PRIORITY ORDER OF THREE FACTORS INTERRUPT]

Order Interrupt factor

Vector Address(H:HEX)

(1) External interrupt-1

10H

(2) Internal interrupt-1 Timer Overflow

20H

(3) Internal interrupt-2 Serial shift register Full/Empty

30H

The External interrupt-1 enabled by PHY5 is started the interrupt process when the rising edge of signal

pulse is input to the external interrupt signal input terminal(EXTI). The External interrupt-1 request flag is re-

set by 'RETI' instruction. When the external interrupt-1 occurs during the standby mode by the HALT

instruction, the External interrupt-1 request signal is latched and its interrupt process is started after that the

standby mode is released.

The Internal interrupt enabled by PHY5 is started the interrupt process when the internal interrupt request flag

is set.

The Timer interrupt request flag is independent of the overflow flag, and it is reset by "RETI" instruction,

(TIMER)START signal of the Timer control register, or RESET signal from the external circuit. Serial Input

Output interrupt request flag is set synchronizing with the transmission end flag when its interrupt is enabled by

PHY5. And the flag is reset by the "RETI" instruction or the RESET signal from the external circuit.

• INTERRUPT CONTROL REGISTER {PHY5 ; (Y'=5)}

[Writing to the Interrupt Control Register]

(MSB) 3

2

1

0 (LSB)

PHY5 −

Serial shift register Full/Empty interrupt

(internal interrupt-2) control bit / 0:Disable

1:Enable

Timer Overflow interrupt

(internal interrupt-1) control bit / 0:Disable

External interrupt-1 control bit / 0:Disable

[Reading from the Interrupt Control Register]

1:Enable

1:Enable

(MSB) 3

2

1

0 (LSB)

PHY5 “0”

Serial shift register Full/Empty interrupt

(internal interrupt-2) / 0:Disable

1:Enable

Timer Overflow interrupt

(internal interrupt-1) / 0:Disable

1:Enable

External interrupt-1/ 0:Disable

1:Enable

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