NJU3502L データシートの表示（PDF） - Japan Radio Corporation
部品番号
コンポーネント説明
一致するリスト
NJU3502L Datasheet PDF : 42 Pages
| |||
NJU3502
Remarks3)In case of the external clock operation at the both of the transmission and reception mode, inputting the
external clock must wait while the 2-instruction execution period after that LSB of Serial Input / Output
control register is set to "1"(START). (one instruction execution period = 1 / fOSC X 6)
If the external clock is input within the 2-instruction execution period, the Serial Input / Output shift
register can not recognize the first SCK. The number of the shift operation is decreased a time, 8 times
to 7.
[Reading from the Serial Input / Output Control Register]
(MSB) 3
2
1
0 (LSB)
PHY1
“0”
The end flag of transmission
Clock mode
SDI(O) direction
/ 0:Busy 1:End
/ 0:Internal 1:External
/ 0:Input 1:Output
Remarks4)The end flag of transmission is set to "1" when the serial data(8 bits) transmission operation is ended.
It is cleared by setting the serial data transmission start signal in the Serial Input /Output control register.
• SERIAL INPUT/OUTPUT SHIFT REGISTER {PHY2 ; (Y'=2)}
The Serial Input / Output Shift register consisted of a 8-bit register operates to set the transmission data
or to get the reception data.
[Writing to the Serial Input / Output Shift Register]
The data in RAM or Accumulator is transferred to the Serial Input / Output Shift register, and it is
loaded into lower 4-bit(b0 to b3) or higher(b4 to b7) in PHY2 in accordance with the condition of LSB
of Y-register.
YLSB=1
(MSB) 3 2 1 0 (LSB) (MSB) 7 6 5 4 3 2 1 0 (LSB)
M(X,Y)
or
AC
8bit Serial
Input/Output register
YLSB=0
PHY2
[Reading from the Serial Input / Output Shift Register]
The Serial Input data is transferred to RAM or Accumulator, it is loaded from lower 4-bit(b0 to b3) or
higher(b4 to b7) of PHY2 in accordance with the condition of LSB of Y-register.
YLSB=1
(MSB) 3 2 1 0 (LSB) (MSB) 7 6 5 4 3 2 1 0 (LSB)
M(X,Y)
or
AC
8bit Serial
Input/Output register
YLSB=0
PHY2
- 24 -
Share Link: 