MAX4561_V1 データシートの表示（PDF） - Maxim Integrated
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MAX4561_V1 Datasheet PDF : 11 Pages
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±15kV ESD-Protected, Low-Voltage,
SPDT/SPST, CMOS Analog Switches
Test Circuits/Timing Diagrams
MAX4561
MAX4568
MAX4569 SWITCH
INPUT
NO
OR NC
IN
LOGIC
GND
INPUT
V+
V+
COM
SWITCH
OUTPUT
VOUT
RL
CL
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
( ) VOUT = VCOM
RL
RL + RON
Figure 1. Switching Time
+3V
LOGIC
INPUT 0
50%
tr < 20ns
tf < 20ns
SWITCH 0
OUTPUT
tOFF
VOUT 0.9 x V0UT
0.9 x VOUT
tON
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
MAX4561
+3V
LOGIC
INPUT
V+
V+
NC
COM
NO
IN
GND
VOUT
RL
CL
CL INCLUDES FIXTURE AND STRAY CAPACITANCE.
Figure 2. Break-Before-Make Interval
+3V
LOGIC
INPUT
50%
0
SWITCH
OUTPUT
(VOUT)
0.9 x VOUT
tBBM
0.9 x VOUT
MAX4561
MAX4568
MAX4569
VGEN
RGEN NC
OR NO
GND
V+
V+
COM
IN
VOUT
CL
VIN = LOGIC INPUT
VOUT
+3V
0
IN
+3V
0
Figure 3. Charge Injection
8
∆VOUT
Q = (∆VOUT)(CL)
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
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