M312L2828ET0 データシートの表示（PDF） - Samsung

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M312L2828ET0

DDR SDRAM Registered Module

Samsung 

256MB, 512MB, 1GB Registered DIMM

DDR SDRAM

184Pin Registered DIMM based on 256Mb E-die (x4, x8)

Ordering Information

Part Number

M383L3223ETS-CAA/A2/B0/A0

M383L6423ETS-CAA/A2/B0/A0

M383L6420ETS-CAA/A2/B0/A0

M383L2828ET1-CAA/A2/B0/A0

M312L3223ETS-CAA/A2/B0/A0

M312L6423ETS-CAA/A2/B0/A0

M312L6420ETS-CAA/A2/B0/A0

M312L2828ET0-CAA/A2/B0/A0

Density

256MB

512MB

512MB

1GB

256MB

512MB

512MB

1GB

Organization

32M x 72

64M x 72

64M x 72

128M x 72

32M x 72

64M x 72

64M x 72

128M x 72

Component Composition

32Mx8( K4H560838E) * 9EA

32Mx8( K4H560838E) * 18EA

64Mx4( K4H560438E) * 18EA

st.128Mx4( K4H510638E) * 18EA

32Mx8( K4H560838E) * 9EA

32Mx8( K4H560838E) * 18EA

64Mx4( K4H560438E) * 18EA

st.128Mx4( K4H510638E) * 18EA

Height

1,700mil

1,700mil

1,700mil

1,700mil

1,200mil

1,200mil

1,200mil

1,200mil

Operating Frequencies

Speed @CL2

Speed @CL2.5

CL-tRCD-tRP

AA(DDR266@CL=2)

133MHz

133MHz

2-2-2

A2(DDR266@CL=2)

133MHz

133MHz

2-3-3

B0(DDR266@CL=2.5)

100MHz

133MHz

2.5-3-3

A0(DDR200@CL=2)

100MHz

-

2-2-2

Feature

• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency 2, 2.5 (clock)

• Programmable Burst length (2, 4, 8)

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

• Serial presence detect with EEPROM

• 1,700mil / 1,200mil height & double sided

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Revision 1.4 February, 2004

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