ISP1561 データシートの表示（PDF） - Philips Electronics

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ISP1561

Hi-Speed USB PCI host controller

Philips Electronics 

Philips Semiconductors

ISP1561

USB PCI host controller

EHCI Host Controller. The system-specific policy can be established by BIOS

initializing this register to a system-specific value. System software uses the

information in this register when enabling devices and ports for remote wake-up.

Table 29: PORTWAKECAP register: bit description

Bit

Symbol

Access Value Description

15 to 0 PORTWAKECAP[15:0] R/W

001FH Port Wake Up Capability Mask: EHCI does not implement this

feature.

8.2.3 Power management registers

Table 30: Power Management registers

Offset

Register

value read from address 34H + 0H

Capability Identifier (Cap_ID)

value read from address 34H + 1H

Next Item Pointer (Next_Item_Ptr)

value read from address 34H + 2H

Power Management Capabilities (PMC)

value read from address 34H + 4H

Power Management Control/Status (PMCSR)

value read from address 34H + 6H

Power Management Control/Status (PMCSR_BSE)

value read from address 34H + 7H

Data

Cap_ID register (address: value read from address 34H + 0H): The Capability

Identifier (Cap_ID) register, when read by the system software as 01H indicates that

the data structure currently being pointed to is the PCI Power Management data

structure. Each function of a PCI device may have only one item in its capability list

with Cap_ID set to 01H. The bit description o the register is given in Table 31.

Table 31: Cap_ID register: bit description

Bit

Symbol

Access

Value

7 to 0 Cap_ID[7:0] R

01H

Description

ID: This field when 01H identifies the linked list item as being the

PCI Power Management registers.

Next_Item_Ptr register (address: value read from address 34H + 1H): The Next

Item Pointer (Next_Item_Ptr) register (see Table 32) describes the location of the next

item in the function’s capability list. The value given is an offset into the function’s PCI

Configuration Space. If the function does not implement any other capabilities

defined by the PCI-SIG for inclusion in the capabilities list, or if power management is

the last item in the list, then this register must be set to 00H.

Table 32: Next_Item_Ptr register: bit description

Bit

Symbol

Access Value Description

7 to 0 Next_Item_Ptr[7:0] R

00H Next Item Pointer: This field provides an offset into the function’s PCI

Configuration Space pointing to the location of the next item in the

function’s capability list. If there are no additional items in the

Capabilities List, this register is set to 00H.

PMC register (address: value read from address 34H + 2H): The Power

Management Capabilities (PMC) register is a two-byte register, and the bit allocation

is given in Table 33. This read-only register provides information on the capabilities of

the function related to power management.

9397 750 10015

Product data

Rev. 01 — 06 February 2003

© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

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