ISP1561 データシートの表示（PDF） - Philips Electronics

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ISP1561

Hi-Speed USB PCI host controller

Philips Electronics 

Philips Semiconductors

ISP1561

USB PCI host controller

Table 12: Class Code register: bit description

Bit

Symbol Description

23 to 16

BCC[7:0]

Base Class Code: 0CH is the base class code assigned to this

byte, and it implies a serial bus controller.

15 to 8

SCC[7:0] Sub-Class Code: 03H is the sub-class code assigned to this byte,

and it implies the USB Host Controller.

7 to 0

RLPI[7:0]

Register-Level Programming Interface: 10H is the programming

interface code assigned to OHCI, which is USB 1.1 specification

compliant. 20H is the programming interface code assigned to

EHCI, which is USB 2.0 specification compliant.

CacheLine Size register (address: 0CH): The CacheLine Size register is a

read/write single byte register that specifies the system cacheline size in units of

DWords. This register must be implemented by master devices that can generate the

Memory Write and Invalidate command. The value in this register is also used by

master devices to determine whether to use Read, Read Line, or Read Multiple

commands for accessing memory.

Slave devices that want to allow memory bursting using a cacheline-wrap addressing

mode must implement this register to know when a burst sequence wraps to the

beginning of the cacheline.

This field must be initialized to logic 0 on activation of RST#. Table 13 shows the bit

description of the CacheLine Size register.

Table 13: CacheLine Size register: bit description

Bit

Symbol

Access

Value

Description

7 to 0 CLS[7:0]

R/W

00H

CacheLine Size: This byte identifies the system cacheline size.

Latency Timer register (address: 0DH): This one-byte register specifies, in units of

PCI bus clocks, the value of the Latency Timer for the PCI bus master. The Latency

Time register bit description is given in Table 14.

This register must be implemented as writable by any master that can burst more

than two data phases. This register may be implemented as read-only for devices that

burst two or fewer data phases, but the fixed value must be limited to 16 or less. The

register must be initialized to logic 0 at RST#, if programmable.

Table 14: Latency Timer register: bit description

Bit

Symbol

Access

Value

Description

7 to 0 LT[7:0]

R/W

00H

Latency Timer: This byte identifies the latency timer.

Header Type register (address: 0EH): The Header Type register identifies the

layout of the second part of the predefined header (beginning at byte 10H in

Configuration Space). It also identifies whether or not the device contains multiple

functions (bit allocation: see Table 15).

Table 15: Header Type register: bit allocation

Bit

7

6

5

4

3

2

1

0

Symbol

MFD

HT[6:0]

Reset

1

0

0

0

0

0

0

0

Access

R

R

R

R

R

R

R

R

9397 750 10015

Product data

Rev. 01 — 06 February 2003

© Koninklijke Philips Electronics N.V. 2003. All rights reserved.

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