ISP1561 データシートの表示（PDF） - Philips Electronics
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ISP1561 Datasheet PDF : 102 Pages
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Philips Semiconductors
ISP1561
USB PCI host controller
Table 9:
Bit
15
14
13
12
11
10 to 9
Status register: bit description
Symbol
Description
DPE
Detected Parity Error: This bit must be set by the device
whenever it detects a parity error, even if the parity error
handling is disabled.
SSE
Signaled System Error: This bit must be set whenever the
device asserts SERR#. Devices that never assert SERR# do not
need to implement this bit.
RMA
Received Master Abort: This bit must be set by a master
device whenever its transaction (except for Special Cycle) is
terminated with Master-Abort. All master devices must
implement this bit.
RTA
Received Target Abort: This bit must be set by a master device
whenever its transaction is terminated with Target-Abort. All
master devices must implement this bit.
STA
Signaled Target Abort: This bit must be set by a target device
whenever it terminates a transaction with Target-Abort. Devices
that never signal Target-Abort do not need to implement this bit.
DEVSELT[1:0] DEVSEL Timing: These bits encode the timing of DEVSEL#.
There are three allowable timings for assertion of DEVSEL#:
8
MDPE
7
FBBC
6
-
00B — for fast
01B — for medium
10B — for slow
11B — is reserved
These bits are read-only and must indicate the slowest time that
a device asserts DEVSEL# for any bus command except
Configuration Read and Configuration Write.
Master Data Parity Error: This bit is implemented by bus
masters. It is set when the following three conditions are met:
• The bus agent asserted PERR# itself (on a read) or observed
PERR# asserted (on a write).
• The agent setting the bit acted as the bus master for the
operation in which error occurred.
• The Parity Error Response bit (in the Command register) is
set.
Fast Back-to-Back Capable: This read-only bit indicates
whether or not the target is capable of accepting fast
back-to-back transactions when the transactions are not to the
same agent. This bit can be set to logic 1 if the device can
accept these transactions and must be set to logic 0 otherwise.
reserved
9397 750 10015
Product data
Rev. 01 — 06 February 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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