IDT82V2048(2010) データシートの表示（PDF） - Integrated Device Technology

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IDT82V2048
(Rev.:2010)

OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT

Integrated Device Technology 

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT

INDUSTRIAL TEMPERATURE RANGES

Table-1 Pin Description (Continued)

Name

TD0/TDP0

TD1/TDP1

TD2/TDP2

TD3/TDP3

TD4/TDP4

TD5/TDP5

TD6/TDP6

TD7/TDP7

BPVI0/TDN0

BPVI1/TDN1

BPVI2/TDN2

BPVI3/TDN3

BPVI4/TDN4

BPVI5/TDN5

BPVI6/TDN6

BPVI7/TDN7

TCLK0

TCLK1

TCLK2

TCLK3

TCLK4

TCLK5

TCLK6

TCLK7

Pin No.

Type

TQFP144 PBGA160

Description

Transmit and Receive Digital Data Interface

TDn: Transmit Data for Channel 0~7

When the device is in Single Rail mode, the NRZ data to be transmitted is input on this pin. Data on TDn is

37

30

N2

L2

sampled into the device on the falling edges of TCLKn, and encoded by AMI or B8ZS/HDB3 line code

rules before being transmitted to the line.

80

73

108

101

8

L13

N13

B13

D13

D2

BPVIn: Bipolar Violation Insertion for Channel 0~7

Bipolar violation insertion is available in Single Rail mode 2 (see Table-2 on page 13 and Table-3 on page

14) with AMI enabled. A low-to-high transition on this pin will make the next logic one to be transmitted on

TDn the same polarity as the previous pulse, and violate the AMI rule. This is for testing.

I

1

B2

TDPn/TDNn: Positive/Negative Transmit Data for Channel 0~7

38

31

79

N3

L3

L12

When the device is in Dual Rail Mode, the NRZ data to be transmitted for positive/negative pulse is input

on this pin. Data on TDPn/TDNn are sampled on the falling edges of TCLKn. The line code in dual rail

mode is as the follow:

72

N12

TDPn

TDNn

Output Pulse

109

B12

0

0

Space

102

D12

0

1

Negative Pulse

7

D3

1

0

Positive Pulse

144

B3

1

1

Space

Pulling pin TDNn high for more than 16 consecutive TCLK clock cycles will configure the corresponding

channel into Single Rail mode 1 (see Table-2 on page 13 and Table-3 on page 14).

TCLKn: Transmit Clock for Channel 0~7

The clock of 1.544 MHz (for T1 mode) or 2.048 MHz (for E1 mode) for transmit is input on this pin. The

transmit data at TDn/TDPn or TDNn is sampled into the device on the falling edges of TCLKn.

Pulling TCLKn high for more than 16 MCLK cycles, the corresponding transmitter is set in Transmit All

Ones (TAOS) state (when MCLK is clocked). In TAOS state, the TAOS generator adopts MCLK as the

clock reference.

If TCLKn is low, the corresponding transmit channel is set into power down state, while driver output ports

become high-Z.

Different combinations of TCLKn and MCLK result in different transmit mode. It is summarized as the fol-

36

N1 lows:

29

L1

MCLK

TCLKn

Transmit Mode

81

L14

Clocked

Clocked Normal operation

I

74

107

N14

B14

Clocked

High (≥

16 MCLK)

Transmit All Ones (TAOS) signals to the line side in the corresponding

transmit channel.

100

D14

Clocked Low (≥ 64 MCLK) The corresponding transmit channel is set into power down state.

9

D1

TCLKn is clocked Normal operation

2

B1

TCLKn is high Transmit All Ones (TAOS) signals to the line side

(≥ 16 TCLK1) in the corresponding transmit channel.

High/Low

TCLK1 is clocked

TCLKn is low

(≥ 64 TCLK1)

Corresponding transmit channel is set into power

down state.

The receive path is not affected by the status of TCLK1. When MCLK

is high, all receive paths just slice the incoming data stream. When

MCLK is low, all the receive paths are powered down.

High/Low

TCLK1 is unavail-

able.

All eight transmitters (TTIPn & TRINGn) will be in high-Z.

5

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