HSP45116AVC-52Z データシートの表示（PDF） - Intersil

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HSP45116AVC-52Z

Numerically Controlled Oscillator/Modulator

Intersil 

HSP45116A

Pin Descriptions (Continued)

NAME

NUMBER

TYPE

DESCRIPTION

PMSEL

39

I Phase Modulation Select Line. This line determines the source of the data clocked into the Phase

Register. When high, the Phase Control Register is selected. When low, the external modulation pins

(MOD0-1) are selected for the most significant two bits and the least significant two bits and the least

significant 14 bits are set to zero. This control is registered by CLK.

RBYTILD

30

I ROM Bypass, Timer Load (active low). Registered by CLK. This input bypasses the sine/ cosine

ROM so that the 16 bit phase adder output and lower 16 bits of the phase accumulator go directly

to the CMAC’s sine and cosine inputs, respectively. It also enables loading of the Timer

Accumulator Register by zeroing the feedback in the accumulator.

PACI

37

I Phase Accumulator Carry Input (active low). A low on this pin causes the phase accumulator to

increment by one in addition to the values in the Phase Accumulator Register and frequency

adder.

PACO

79

O Phase Accumulator Carry Output. Active low and registered by CLK. A low on this output

indicates that the phase accumulator has overflowed, i.e., the end of one sine/cosine cycle has

been reached.

TICO

33

O Time Interval Accumulator Carry Output. Active low, registered by CLK. This output goes low

when a carry is generated by the time interval accumulator. This function is provided to time out

control events such as synchronizing register clocking to data timing.

RIN0-18

2-6, 8-19, 21, 23

I Real Input Data Bus. RIN18 is the MSB. This is the external real component into the complex

multiplier. The bus is clocked into the real Input Data Register by CLK when ENI is asserted. Two’s

complement.

IMIN0-18

1, 138-142, 144,

146-156, 158

I Imaginary Input Data Bus. IMIN18 is the MSB. This is the external imaginary component into the

complex multiplier. The bus is clocked into the real Input Data Register by CLK when ENI is

asserted. Two’s complement.

SH0-1

24, 25

I Shift Control Inputs. These lines control the input shifters of the RIN and IIN inputs of the complex

multiplier. The shift controls are common to the shifters on both of the busses.

SH1

SH0

0

0

0

1

1

0

1

1

SELECTED BITS

RIN0-15, IMIN0-15

RIN1-16, IMIN1-16

RIN2-17, IMIN2-17

RIN3-18, IMIN3-18

ACC

26

BINFMT

31

PEAK

29

I Accumulate/Dump Control. This input controls the complex accumulators and their holding

registers. When high, the accumulators accumulate and the holding registers are disabled. When

low, the feedback in the accumulators is zeroed to cause the accumulators to load.

The holding registers are enabled to clock in the results of the accumulation. This input is

registered by CLK.

I This input is used to convert the two’s complement output to offset binary (unsigned) for

applications using D/A converters. When low, bits RO19 and IO19 are inverted from the internal

two’s complement representation. This input is registered by CLK.

I This input enables the peak detect feature of the block floating point detector. When high, the

maximum bit growth in the Output Holding Registers is encoded and output on the DET0-1 pins.

When the PEAK input is asserted, the block floating point detector output will track the maximum

growth in the holding registers, including the data in the Holding Registers at the time that PEAK

is activated.

5

FN4156.4

May 7, 2007

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