DM9106 データシートの表示（PDF） - Davicom Semiconductor, Inc.

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DM9106

10/100 Mbps 3-port Ethernet Switch Controller with PCI Interface

Davicom Semiconductor, Inc. 

DM9106

3-port switch with PCI Interface

5. Pin Description

I = Input, O = Output, I/O = Input / Output, O/D = Open Drain, P = Power, PD=internal pull-low (about 50K Ohm)

# = asserted Low

5.1 PCI Bus interface

Pin No.

Pin Name

I/O

Description

2

14

15

16

17

19

20

22

23

1,13,25,36

IDSEL

FRAME#

IRDY#

TRDY#

DEVSEL#

STOP#

PERR#

SERR#

PAR

C/BE3#

C/BE2#

C/BE1#

C/BE0#

I Initialization Device Select

This signal is asserted high during the Configuration Space

read/write access.

I/O Cycle Frame

This signal is driven low by the DM9106 master mode to

indicate the beginning and duration of a bus transaction.

I/O Initiator Ready

This signal is driven low when the master is ready to complete

the current data phase of the transaction. A data phase is

completed on any clock when both IRDY# and TRDY# are

sampled asserted.

I/O Target Ready

This signal is driven low when the target is ready to complete

the current data phase of the transaction. During a read, it

indicates that valid data is asserted. During a write, it indicates

that the target is prepared to accept data.

I/O Device Select

The DM9106 asserts the signal low when it recognizes its

target address after FRAME# is asserted. As a bus master, the

DM9106 will sample this signal which insures its destination

address of the data transfer is recognized by a target.

I/O Stop

This signal is asserted low by the target device to request the

master device to stop the current transaction.

I/O Parity Error

The DM9106 as a master or slave will assert this signal low to

indicate a parity error on any incoming data.

I/O System Error

This signal is asserted low when address parity is detected with

enabled PCICS bit31 (detected parity error.) The system error

asserts two clock cycles after the falling address if an address

parity error is detected.

I/O Parity

This signal indicates even parity across AD0~AD31 and

C/BE0#~C/BE3# including the PAR pin. This signal is an

output for the master and an input for the slave device. It is

stable and valid one clock after the address phase.

I/O Bus Command/Byte Enable

During the address phase, these signals define the bus

command or the type of bus transaction that will take place.

During the data phase these pins indicate which byte lanes

contain valid data. C/BE0# applies to bit7-0 and C/BE3#

applies to bit31-24.

Preliminary datasheet

11

DM9106-DS-P01

July 9, 2009

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